Commit fa75ad14 authored by Yongbok Kim's avatar Yongbok Kim Committed by Aleksandar Markovic
Browse files

target/mips: Add CP0 PWField register 



Add PWField register (CP0 Register 5, Select 6).

The PWField register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

MIPS64:
BDI  (37..32) - Base Directory index
GDI  (29..24) - Global Directory index
UDI  (23..18) - Upper Directory index
MDI  (17..12) - Middle Directory index
PTI  (11..6 ) - Page Table index
PTEI ( 5..0 ) - Page Table Entry shift

MIPS32:
GDW  (29..24) - Global Directory index
UDW  (23..18) - Upper Directory index
MDW  (17..12) - Middle Directory index
PTW  (11..6 ) - Page Table index
PTEW ( 5..0 ) - Page Table Entry shift

Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarYongbok Kim <yongbok.kim@mips.com>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 5e31fdd5

target/mips/cpu.h

+15 −0
Original line number Diff line number Diff line
@@ -417,6 +417,21 @@ struct CPUMIPSState { 
#define CP0SC2_XR_MASK  (0xFFULL << CP0SC2_XR)

#define CP0SC2_MASK     (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)

    target_ulong CP0_PWBase;

    target_ulong CP0_PWField;

#if defined(TARGET_MIPS64)

#define CP0PF_BDI  32    /* 37..32 */

#define CP0PF_GDI  24    /* 29..24 */

#define CP0PF_UDI  18    /* 23..18 */

#define CP0PF_MDI  12    /* 17..12 */

#define CP0PF_PTI  6     /* 11..6  */

#define CP0PF_PTEI 0     /*  5..0  */

#else

#define CP0PF_GDW  24    /* 29..24 */

#define CP0PF_UDW  18    /* 23..18 */

#define CP0PF_MDW  12    /* 17..12 */

#define CP0PF_PTW  6     /* 11..6  */

#define CP0PF_PTEW 0     /*  5..0  */

#endif

/*

 * CP0 Register 6

 */

target/mips/helper.h

+1 −0
Original line number Diff line number Diff line
@@ -120,6 +120,7 @@ DEF_HELPER_2(mtc0_pagegrain, void, env, tl) 
DEF_HELPER_2(mtc0_segctl0, void, env, tl)

DEF_HELPER_2(mtc0_segctl1, void, env, tl)

DEF_HELPER_2(mtc0_segctl2, void, env, tl)

DEF_HELPER_2(mtc0_pwfield, void, env, tl)

DEF_HELPER_2(mtc0_wired, void, env, tl)

DEF_HELPER_2(mtc0_srsconf0, void, env, tl)

DEF_HELPER_2(mtc0_srsconf1, void, env, tl)

target/mips/machine.c

+3 −2
Original line number Diff line number Diff line
@@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = { 


const VMStateDescription vmstate_mips_cpu = {

    .name = "cpu",

    .version_id = 12,

    .minimum_version_id = 12,

    .version_id = 13,

    .minimum_version_id = 13,

    .post_load = cpu_post_load,

    .fields = (VMStateField[]) {

        /* Active TC */
@@ -257,6 +257,7 @@ const VMStateDescription vmstate_mips_cpu = { 
        VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),

        VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),

        VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),

        VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),

        VMSTATE_INT32(env.CP0_Wired, MIPSCPU),

        VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),

        VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),

target/mips/op_helper.c

+62 −0
Original line number Diff line number Diff line
@@ -1445,6 +1445,68 @@ void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1) 
    tlb_flush(cs);

}



void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)

{

#if defined(TARGET_MIPS64)

    uint64_t mask = 0x3F3FFFFFFFULL;

    uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;

    uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;



    if ((env->insn_flags & ISA_MIPS32R6)) {

        if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {

            mask &= ~(0x3FULL << CP0PF_BDI);

        }

        if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {

            mask &= ~(0x3FULL << CP0PF_GDI);

        }

        if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {

            mask &= ~(0x3FULL << CP0PF_UDI);

        }

        if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {

            mask &= ~(0x3FULL << CP0PF_MDI);

        }

        if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {

            mask &= ~(0x3FULL << CP0PF_PTI);

        }

    }

    env->CP0_PWField = arg1 & mask;



    if ((new_ptei >= 32) ||

            ((env->insn_flags & ISA_MIPS32R6) &&

                    (new_ptei == 0 || new_ptei == 1))) {

        env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |

                (old_ptei << CP0PF_PTEI);

    }

#else

    uint32_t mask = 0x3FFFFFFF;

    uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;

    uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;



    if ((env->insn_flags & ISA_MIPS32R6)) {

        if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {

            mask &= ~(0x3F << CP0PF_GDW);

        }

        if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {

            mask &= ~(0x3F << CP0PF_UDW);

        }

        if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {

            mask &= ~(0x3F << CP0PF_MDW);

        }

        if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {

            mask &= ~(0x3F << CP0PF_PTW);

        }

    }

    env->CP0_PWField = arg1 & mask;



    if ((new_ptew >= 32) ||

            ((env->insn_flags & ISA_MIPS32R6) &&

                    (new_ptew == 0 || new_ptew == 1))) {

        env->CP0_PWField = (env->CP0_PWField & ~0x3F) |

                (old_ptew << CP0PF_PTEW);

    }

#endif

}



void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)

{

    if (env->insn_flags & ISA_MIPS32R6) {

target/mips/translate.c

+20 −0
Original line number Diff line number Diff line
@@ -6106,6 +6106,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));

            rn = "PWBase";

            break;

        case 6:

            check_pw(ctx);

            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));

            rn = "PWField";

            break;

        default:

            goto cp0_unimplemented;

        }
@@ -6812,6 +6817,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));

            rn = "PWBase";

            break;

        case 6:

            check_pw(ctx);

            gen_helper_mtc0_pwfield(cpu_env, arg);

            rn = "PWField";

            break;

        default:

            goto cp0_unimplemented;

        }
@@ -7527,6 +7537,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));

            rn = "PWBase";

            break;

        case 6:

            check_pw(ctx);

            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));

            rn = "PWField";

            break;

        default:

            goto cp0_unimplemented;

        }
@@ -8215,6 +8230,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));

            rn = "PWBase";

            break;

        case 6:

            check_pw(ctx);

            gen_helper_mtc0_pwfield(cpu_env, arg);

            rn = "PWField";

            break;

        default:

            goto cp0_unimplemented;

        }