Commit 208d92df authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190311' into staging 



s390x update:
- clean up LowCore definition
- first part of vector instruction support for tcg

# gpg: Signature made Mon 11 Mar 2019 08:59:02 GMT
# gpg:                using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF
# gpg:                issuer "cohuck@redhat.com"
# gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown]
# gpg:                 aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full]
# gpg:                 aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full]
# gpg:                 aka "Cornelia Huck <cohuck@kernel.org>" [unknown]
# gpg:                 aka "Cornelia Huck <cohuck@redhat.com>" [unknown]
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0  18CE DECF 6B93 C6F0 2FAF

* remotes/cohuck/tags/s390x-20190311: (33 commits)
  s390x/tcg: Implement VECTOR UNPACK *
  s390x/tcg: Implement VECTOR STORE WITH LENGTH
  s390x/tcg: Implement VECTOR STORE MULTIPLE
  s390x/tcg: Implement VECTOR STORE ELEMENT
  s390x/tcg: Implement VECTOR STORE
  s390x/tcg: Provide probe_write_access helper
  s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
  s390x/tcg: Implement VECTOR SELECT
  s390x/tcg: Implement VECTOR SCATTER ELEMENT
  s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
  s390x/tcg: Implement VECTOR REPLICATE
  s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
  s390x/tcg: Implement VECTOR PERMUTE
  s390x/tcg: Implement VECTOR PACK *
  s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
  s390x/tcg: Implement VECTOR LOAD WITH LENGTH
  s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
  s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
  s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
  s390x/tcg: Implement VECTOR LOAD MULTIPLE
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 2e35c773 2c7590c8

target/s390x/Makefile.objs

+1 −0
Original line number Diff line number Diff line 
obj-y += cpu.o cpu_models.o cpu_features.o gdbstub.o interrupt.o helper.o

obj-$(CONFIG_TCG) += translate.o cc_helper.o excp_helper.o fpu_helper.o

obj-$(CONFIG_TCG) += int_helper.o mem_helper.o misc_helper.o crypto_helper.o

obj-$(CONFIG_TCG) += vec_helper.o

obj-$(CONFIG_SOFTMMU) += machine.o ioinst.o arch_dump.o mmu_helper.o diag.o

obj-$(CONFIG_SOFTMMU) += sigp.o

obj-$(CONFIG_KVM) += kvm.o

target/s390x/cpu.h

+7 −0
Original line number Diff line number Diff line
@@ -257,6 +257,7 @@ extern const struct VMStateDescription vmstate_s390_cpu; 
/* PSW defines */

#undef PSW_MASK_PER

#undef PSW_MASK_UNUSED_2

#undef PSW_MASK_UNUSED_3

#undef PSW_MASK_DAT

#undef PSW_MASK_IO

#undef PSW_MASK_EXT
@@ -276,6 +277,7 @@ extern const struct VMStateDescription vmstate_s390_cpu; 


#define PSW_MASK_PER            0x4000000000000000ULL

#define PSW_MASK_UNUSED_2       0x2000000000000000ULL

#define PSW_MASK_UNUSED_3       0x1000000000000000ULL

#define PSW_MASK_DAT            0x0400000000000000ULL

#define PSW_MASK_IO             0x0200000000000000ULL

#define PSW_MASK_EXT            0x0100000000000000ULL
@@ -323,12 +325,14 @@ extern const struct VMStateDescription vmstate_s390_cpu; 


/* we'll use some unused PSW positions to store CR flags in tb flags */

#define FLAG_MASK_AFP           (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)

#define FLAG_MASK_VECTOR        (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)



/* Control register 0 bits */

#define CR0_LOWPROT             0x0000000010000000ULL

#define CR0_SECONDARY           0x0000000004000000ULL

#define CR0_EDAT                0x0000000000800000ULL

#define CR0_AFP                 0x0000000000040000ULL

#define CR0_VECTOR              0x0000000000020000ULL

#define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL

#define CR0_EXTERNAL_CALL_SC    0x0000000000002000ULL

#define CR0_CKC_SC              0x0000000000000800ULL
@@ -373,6 +377,9 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 
    if (env->cregs[0] & CR0_AFP) {

        *flags |= FLAG_MASK_AFP;

    }

    if (env->cregs[0] & CR0_VECTOR) {

        *flags |= FLAG_MASK_VECTOR;

    }

}



/* PER bits from control register 9 */

target/s390x/helper.h

+21 −0
Original line number Diff line number Diff line
@@ -123,6 +123,27 @@ DEF_HELPER_4(cu42, i32, env, i32, i32, i32) 
DEF_HELPER_5(msa, i32, env, i32, i32, i32, i32)

DEF_HELPER_FLAGS_1(stpt, TCG_CALL_NO_RWG, i64, env)

DEF_HELPER_FLAGS_1(stck, TCG_CALL_NO_RWG_SE, i64, env)

DEF_HELPER_FLAGS_3(probe_write_access, TCG_CALL_NO_WG, void, env, i64, i64)



/* === Vector Support Instructions === */

DEF_HELPER_FLAGS_4(vll, TCG_CALL_NO_WG, void, env, ptr, i64, i64)

DEF_HELPER_FLAGS_4(gvec_vpk16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)

DEF_HELPER_FLAGS_4(gvec_vpk32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)

DEF_HELPER_FLAGS_4(gvec_vpk64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)

DEF_HELPER_FLAGS_4(gvec_vpks16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)

DEF_HELPER_FLAGS_4(gvec_vpks32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)

DEF_HELPER_FLAGS_4(gvec_vpks64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)

DEF_HELPER_5(gvec_vpks_cc16, void, ptr, cptr, cptr, env, i32)

DEF_HELPER_5(gvec_vpks_cc32, void, ptr, cptr, cptr, env, i32)

DEF_HELPER_5(gvec_vpks_cc64, void, ptr, cptr, cptr, env, i32)

DEF_HELPER_FLAGS_4(gvec_vpkls16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)

DEF_HELPER_FLAGS_4(gvec_vpkls32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)

DEF_HELPER_FLAGS_4(gvec_vpkls64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)

DEF_HELPER_5(gvec_vpkls_cc16, void, ptr, cptr, cptr, env, i32)

DEF_HELPER_5(gvec_vpkls_cc32, void, ptr, cptr, cptr, env, i32)

DEF_HELPER_5(gvec_vpkls_cc64, void, ptr, cptr, cptr, env, i32)

DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)

DEF_HELPER_FLAGS_4(vstl, TCG_CALL_NO_WG, void, env, cptr, i64, i64)



#ifndef CONFIG_USER_ONLY

DEF_HELPER_3(servc, i32, env, i64, i64)

target/s390x/insn-data.def

+82 −0
Original line number Diff line number Diff line
@@ -972,6 +972,88 @@ 
    D(0xb93e, KIMD,    RRE,   MSA,  0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KIMD)

    D(0xb93f, KLMD,    RRE,   MSA,  0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KLMD)



/* === Vector Support Instructions === */



/* VECTOR GATHER ELEMENT */

    E(0xe713, VGEF,    VRV,   V,   la2, 0, 0, 0, vge, 0, ES_32, IF_VEC)

    E(0xe712, VGEG,    VRV,   V,   la2, 0, 0, 0, vge, 0, ES_64, IF_VEC)

/* VECTOR GENERATE BYTE MASK */

    F(0xe744, VGBM,    VRI_a, V,   0, 0, 0, 0, vgbm, 0, IF_VEC)

/* VECTOR GENERATE MASK */

    F(0xe746, VGM,     VRI_b, V,   0, 0, 0, 0, vgm, 0, IF_VEC)

/* VECTOR LOAD */

    F(0xe706, VL,      VRX,   V,   la2, 0, 0, 0, vl, 0, IF_VEC)

    F(0xe756, VLR,     VRR_a, V,   0, 0, 0, 0, vlr, 0, IF_VEC)

/* VECTOR LOAD AND REPLICATE */

    F(0xe705, VLREP,   VRX,   V,   la2, 0, 0, 0, vlrep, 0, IF_VEC)

/* VECTOR LOAD ELEMENT */

    E(0xe700, VLEB,    VRX,   V,   la2, 0, 0, 0, vle, 0, ES_8, IF_VEC)

    E(0xe701, VLEH,    VRX,   V,   la2, 0, 0, 0, vle, 0, ES_16, IF_VEC)

    E(0xe703, VLEF,    VRX,   V,   la2, 0, 0, 0, vle, 0, ES_32, IF_VEC)

    E(0xe702, VLEG,    VRX,   V,   la2, 0, 0, 0, vle, 0, ES_64, IF_VEC)

/* VECTOR LOAD ELEMENT IMMEDIATE */

    E(0xe740, VLEIB,   VRI_a, V,   0, 0, 0, 0, vlei, 0, ES_8, IF_VEC)

    E(0xe741, VLEIH,   VRI_a, V,   0, 0, 0, 0, vlei, 0, ES_16, IF_VEC)

    E(0xe743, VLEIF,   VRI_a, V,   0, 0, 0, 0, vlei, 0, ES_32, IF_VEC)

    E(0xe742, VLEIG,   VRI_a, V,   0, 0, 0, 0, vlei, 0, ES_64, IF_VEC)

/* VECTOR LOAD GR FROM VR ELEMENT */

    F(0xe721, VLGV,    VRS_c, V,   la2, 0, r1, 0, vlgv, 0, IF_VEC)

/* VECTOR LOAD LOGICAL ELEMENT AND ZERO */

    F(0xe704, VLLEZ,   VRX,   V,   la2, 0, 0, 0, vllez, 0, IF_VEC)

/* VECTOR LOAD MULTIPLE */

    F(0xe736, VLM,     VRS_a, V,   la2, 0, 0, 0, vlm, 0, IF_VEC)

/* VECTOR LOAD TO BLOCK BOUNDARY */

    F(0xe707, VLBB,    VRX,   V,   la2, 0, 0, 0, vlbb, 0, IF_VEC)

/* VECTOR LOAD VR ELEMENT FROM GR */

    F(0xe722, VLVG,    VRS_b, V,   la2, r3, 0, 0, vlvg, 0, IF_VEC)

/* VECTOR LOAD VR FROM GRS DISJOINT */

    F(0xe762, VLVGP,   VRR_f, V,   r2, r3, 0, 0, vlvgp, 0, IF_VEC)

/* VECTOR LOAD WITH LENGTH */

    F(0xe737, VLL,     VRS_b, V,   la2, r3_32u, 0, 0, vll, 0, IF_VEC)

/* VECTOR MERGE HIGH */

    F(0xe761, VMRH,    VRR_c, V,   0, 0, 0, 0, vmr, 0, IF_VEC)

/* VECTOR MERGE LOW */

    F(0xe760, VMRL,    VRR_c, V,   0, 0, 0, 0, vmr, 0, IF_VEC)

/* VECTOR PACK */

    F(0xe794, VPK,     VRR_c, V,   0, 0, 0, 0, vpk, 0, IF_VEC)

/* VECTOR PACK SATURATE */

    F(0xe797, VPKS,    VRR_b, V,   0, 0, 0, 0, vpk, 0, IF_VEC)

/* VECTOR PACK LOGICAL SATURATE */

    F(0xe795, VPKLS,   VRR_b, V,   0, 0, 0, 0, vpk, 0, IF_VEC)

    F(0xe78c, VPERM,   VRR_e, V,   0, 0, 0, 0, vperm, 0, IF_VEC)

/* VECTOR PERMUTE DOUBLEWORD IMMEDIATE */

    F(0xe784, VPDI,    VRR_c, V,   0, 0, 0, 0, vpdi, 0, IF_VEC)

/* VECTOR REPLICATE */

    F(0xe74d, VREP,    VRI_c, V,   0, 0, 0, 0, vrep, 0, IF_VEC)

/* VECTOR REPLICATE IMMEDIATE */

    F(0xe745, VREPI,   VRI_a, V,   0, 0, 0, 0, vrepi, 0, IF_VEC)

/* VECTOR SCATTER ELEMENT */

    E(0xe71b, VSCEF,   VRV,   V,   la2, 0, 0, 0, vsce, 0, ES_32, IF_VEC)

    E(0xe71a, VSCEG,   VRV,   V,   la2, 0, 0, 0, vsce, 0, ES_64, IF_VEC)

/* VECTOR SELECT */

    F(0xe78d, VSEL,    VRR_e, V,   0, 0, 0, 0, vsel, 0, IF_VEC)

/* VECTOR SIGN EXTEND TO DOUBLEWORD */

    F(0xe75f, VSEG,    VRR_a, V,   0, 0, 0, 0, vseg, 0, IF_VEC)

/* VECTOR STORE */

    F(0xe70e, VST,     VRX,   V,   la2, 0, 0, 0, vst, 0, IF_VEC)

/* VECTOR STORE ELEMENT */

    E(0xe708, VSTEB,   VRX,   V,   la2, 0, 0, 0, vste, 0, ES_8, IF_VEC)

    E(0xe709, VSTEH,   VRX,   V,   la2, 0, 0, 0, vste, 0, ES_16, IF_VEC)

    E(0xe70b, VSTEF,   VRX,   V,   la2, 0, 0, 0, vste, 0, ES_32, IF_VEC)

    E(0xe70a, VSTEG,   VRX,   V,   la2, 0, 0, 0, vste, 0, ES_64, IF_VEC)

/* VECTOR STORE MULTIPLE */

    F(0xe73e, VSTM,    VRS_a, V,   la2, 0, 0, 0, vstm, 0, IF_VEC)

/* VECTOR STORE WITH LENGTH */

    F(0xe73f, VSTL,    VRS_b, V,   la2, r3_32u, 0, 0, vstl, 0, IF_VEC)

/* VECTOR UNPACK HIGH */

    F(0xe7d7, VUPH,    VRR_a, V,   0, 0, 0, 0, vup, 0, IF_VEC)

/* VECTOR UNPACK LOGICAL HIGH */

    F(0xe7d5, VUPLH,   VRR_a, V,   0, 0, 0, 0, vup, 0, IF_VEC)

/* VECTOR UNPACK LOW */

    F(0xe7d6, VUPL,    VRR_a, V,   0, 0, 0, 0, vup, 0, IF_VEC)

/* VECTOR UNPACK LOGICAL LOW */

    F(0xe7d4, VUPLL,   VRR_a, V,   0, 0, 0, 0, vup, 0, IF_VEC)



#ifndef CONFIG_USER_ONLY

/* COMPARE AND SWAP AND PURGE */

    E(0xb250, CSP,     RRE,   Z,   r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV)

target/s390x/insn-format.def

+25 −0
Original line number Diff line number Diff line
@@ -54,3 +54,28 @@ F4(SS_e, R(1, 8), BD(2,16,20), R(3,12), BD(4,32,36)) 
F3(SS_f,  BD(1,16,20), L(2,8,8),    BD(2,32,36))

F2(SSE,   BD(1,16,20), BD(2,32,36))

F3(SSF,   BD(1,16,20), BD(2,32,36), R(3,8))

F3(VRI_a, V(1,8),      I(2,16,16),  M(3,32))

F4(VRI_b, V(1,8),      I(2,16,8),   I(3,24,8),   M(4,32))

F4(VRI_c, V(1,8),      V(3,12),     I(2,16,16),  M(4,32))

F5(VRI_d, V(1,8),      V(2,12),     V(3,16),     I(4,24,8),   M(5,32))

F5(VRI_e, V(1,8),      V(2,12),     I(3,16,12),  M(5,28),     M(4,32))

F5(VRI_f, V(1,8),      V(2,12),     V(3,16),     M(5,24),     I(4,28,8))

F5(VRI_g, V(1,8),      V(2,12),     I(4,16,8),   M(5,24),     I(3,28,8))

F3(VRI_h, V(1,8),      I(2,16,16),  I(3,32,4))

F4(VRI_i, V(1,8),      R(2,12),     M(4,24),     I(3,28,8))

F5(VRR_a, V(1,8),      V(2,12),     M(5,24),     M(4,28),     M(3,32))

F5(VRR_b, V(1,8),      V(2,12),     V(3,16),     M(5,24),     M(4,32))

F6(VRR_c, V(1,8),      V(2,12),     V(3,16),     M(6,24),     M(5,28),  M(4,32))

F6(VRR_d, V(1,8),      V(2,12),     V(3,16),     M(5,20),     M(6,24),  V(4,32))

F6(VRR_e, V(1,8),      V(2,12),     V(3,16),     M(6,20),     M(5,28),  V(4,32))

F3(VRR_f, V(1,8),      R(2,12),     R(3,16))

F1(VRR_g, V(1,12))

F3(VRR_h, V(1,12),     V(2,16),     M(3,24))

F3(VRR_i, R(1,8),      V(2,12),     M(3,24))

F4(VRS_a, V(1,8),      V(3,12),     BD(2,16,20), M(4,32))

F4(VRS_b, V(1,8),      R(3,12),     BD(2,16,20), M(4,32))

F4(VRS_c, R(1,8),      V(3,12),     BD(2,16,20), M(4,32))

F3(VRS_d, R(3,12),     BD(2,16,20), V(1,32))

F4(VRV,   V(1,8),      V(2,12),     BD(2,16,20), M(3,32))

F3(VRX,   V(1,8),      BXD(2),      M(3,32))

F3(VSI,   I(3,8,8),    BD(2,16,20), V(1,32))