Commit 2077fef9 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180125' into staging 



target-arm queue:
 * target/arm: Fix address truncation in 64-bit pagetable walks
 * i.MX: Fix FEC/ENET receive functions
 * target/arm: preparatory refactoring for SVE emulation
 * hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and pending"
 * hw/intc/arm_gic: Fix C_RPR value on idle priority
 * hw/intc/arm_gic: Fix group priority computation for group 1 IRQs
 * hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1
 * hw/arm/virt: Check that the CPU realize method succeeded
 * sdhci: fix a NULL pointer dereference due to uninitialized AddressSpace object
 * xilinx_spips: Correct usage of an uninitialized local variable
 * pl110: Implement vertical compare/next base interrupts

# gpg: Signature made Thu 25 Jan 2018 12:59:25 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180125: (21 commits)
  pl110: Implement vertical compare/next base interrupts
  xilinx_spips: Correct usage of an uninitialized local variable
  sdhci: fix a NULL pointer dereference due to uninitialized AddresSpace object
  hw/arm/virt: Check that the CPU realize method succeeded
  hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1
  hw/intc/arm_gic: Fix group priority computation for group 1 IRQs
  hw/intc/arm_gic: Fix C_RPR value on idle priority
  hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and pending"
  target/arm: Simplify fp_exception_el for user-only
  target/arm: Hoist store to flags output in cpu_get_tb_cpu_state
  target/arm: Move cpu_get_tb_cpu_state out of line
  target/arm: Add ARM_FEATURE_SVE
  vmstate: Add VMSTATE_UINT64_SUB_ARRAY
  target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers
  target/arm: Change the type of vfp.regs
  target/arm: Use pointers in neon tbl helper
  target/arm: Use pointers in neon zip/uzp helpers
  target/arm: Use pointers in crypto helpers
  target/arm: Mark disas_set_insn_syndrome inline
  i.MX: Fix FEC/ENET receive funtions
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents a3f9362a 24da047a

hw/arm/virt.c

+1 −1
Original line number Diff line number Diff line
@@ -1404,7 +1404,7 @@ static void machvirt_init(MachineState *machine) 
                                     "secure-memory", &error_abort);

        }



        object_property_set_bool(cpuobj, true, "realized", NULL);

        object_property_set_bool(cpuobj, true, "realized", &error_fatal);

        object_unref(cpuobj);

    }

    fdt_add_timer_nodes(vms);

hw/display/pl110.c

+29 −1
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include "ui/console.h"

#include "framebuffer.h"

#include "ui/pixel_ops.h"

#include "qemu/timer.h"

#include "qemu/log.h"



#define PL110_CR_EN   0x001
@@ -19,6 +20,8 @@ 
#define PL110_CR_BEBO 0x200

#define PL110_CR_BEPO 0x400

#define PL110_CR_PWR  0x800

#define PL110_IE_NB   0x004

#define PL110_IE_VC   0x008



enum pl110_bppmode

{
@@ -50,6 +53,7 @@ typedef struct PL110State { 
    MemoryRegion iomem;

    MemoryRegionSection fbsection;

    QemuConsole *con;

    QEMUTimer *vblank_timer;



    int version;

    uint32_t timing[4];
@@ -320,7 +324,24 @@ static void pl110_resize(PL110State *s, int width, int height) 
/* Update interrupts.  */

static void pl110_update(PL110State *s)

{

  /* TODO: Implement interrupts.  */

    /* Raise IRQ if enabled and any status bit is 1 */

    if (s->int_status & s->int_mask) {

        qemu_irq_raise(s->irq);

    } else {

        qemu_irq_lower(s->irq);

    }

}



static void pl110_vblank_interrupt(void *opaque)

{

    PL110State *s = opaque;



    /* Fire the vertical compare and next base IRQs and re-arm */

    s->int_status |= (PL110_IE_NB | PL110_IE_VC);

    timer_mod(s->vblank_timer,

              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +

                                NANOSECONDS_PER_SECOND / 60);

    pl110_update(s);

}



static uint64_t pl110_read(void *opaque, hwaddr offset,
@@ -429,6 +450,11 @@ static void pl110_write(void *opaque, hwaddr offset, 
        s->bpp = (val >> 1) & 7;

        if (pl110_enabled(s)) {

            qemu_console_resize(s->con, s->cols, s->rows);

            timer_mod(s->vblank_timer,

                      qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +

                                        NANOSECONDS_PER_SECOND / 60);

        } else {

            timer_del(s->vblank_timer);

        }

        break;

    case 10: /* LCDICR */
@@ -474,6 +500,8 @@ static void pl110_realize(DeviceState *dev, Error **errp) 
    memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);

    sysbus_init_mmio(sbd, &s->iomem);

    sysbus_init_irq(sbd, &s->irq);

    s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,

                                   pl110_vblank_interrupt, s);

    qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);

    s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);

}

hw/intc/arm_gic.c

+21 −4
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ void gic_update(GICState *s) 
        best_irq = 1023;

        for (irq = 0; irq < s->num_irq; irq++) {

            if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) &&

                (!GIC_TEST_ACTIVE(irq, cm)) &&

                (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) {

                if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {

                    best_prio = GIC_GET_PRIORITY(irq, cpu);
@@ -255,7 +256,8 @@ static int gic_get_group_priority(GICState *s, int cpu, int irq) 
    if (gic_has_groups(s) &&

        !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) &&

        GIC_TEST_GROUP(irq, (1 << cpu))) {

        bpr = s->abpr[cpu];

        bpr = s->abpr[cpu] - 1;

        assert(bpr >= 0);

    } else {

        bpr = s->bpr[cpu];

    }
@@ -503,6 +505,11 @@ static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 


static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs)

{

    if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) {

        /* Idle priority */

        return 0xff;

    }



    if (s->security_extn && !attrs.secure) {

        if (s->running_priority[cpu] & 0x80) {

            /* Running priority in upper half of range: return the Non-secure
@@ -1205,8 +1212,13 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 
        break;

    case 0x08: /* Binary Point */

        if (s->security_extn && !attrs.secure) {

            if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) {

                /* NS view of BPR when CBPR is 1 */

                *data = MIN(s->bpr[cpu] + 1, 7);

            } else {

                /* BPR is banked. Non-secure copy stored in ABPR. */

                *data = s->abpr[cpu];

            }

        } else {

            *data = s->bpr[cpu];

        }
@@ -1279,7 +1291,12 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 
        break;

    case 0x08: /* Binary Point */

        if (s->security_extn && !attrs.secure) {

            if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) {

                /* WI when CBPR is 1 */

                return MEMTX_OK;

            } else {

                s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR);

            }

        } else {

            s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR);

        }

hw/net/imx_fec.c

+2 −6
Original line number Diff line number Diff line
@@ -595,19 +595,16 @@ static void imx_eth_do_tx(IMXFECState *s, uint32_t index) 
static void imx_eth_enable_rx(IMXFECState *s, bool flush)

{

    IMXFECBufDesc bd;

    bool rx_ring_full;



    imx_fec_read_bd(&bd, s->rx_descriptor);



    rx_ring_full = !(bd.flags & ENET_BD_E);

    s->regs[ENET_RDAR] = (bd.flags & ENET_BD_E) ? ENET_RDAR_RDAR : 0;



    if (rx_ring_full) {

    if (!s->regs[ENET_RDAR]) {

        FEC_PRINTF("RX buffer full\n");

    } else if (flush) {

        qemu_flush_queued_packets(qemu_get_queue(s->nic));

    }



    s->regs[ENET_RDAR] = rx_ring_full ? 0 : ENET_RDAR_RDAR;

}



static void imx_eth_reset(DeviceState *d)
@@ -866,7 +863,6 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, 
    case ENET_RDAR:

        if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) {

            if (!s->regs[index]) {

                s->regs[index] = ENET_RDAR_RDAR;

                imx_eth_enable_rx(s, true);

            }

        } else {

hw/sd/sdhci.c

+1 −0
Original line number Diff line number Diff line
@@ -1388,6 +1388,7 @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) 
    }



    if (s->dma_mr) {

        s->dma_as = &s->sysbus_dma_as;

        address_space_init(s->dma_as, s->dma_mr, "sdhci-dma");

    } else {

        /* use system_memory() if property "dma" not set */