Commit 1f5c00cf authored by Alex Bennée's avatar Alex Bennée
Browse files

qom/cpu: move tlb_flush to cpu_common_reset 



It is a common thing amongst the various cpu reset functions want to
flush the SoftMMU's TLB entries. This is done either by calling
tlb_flush directly or by way of a general memset of the CPU
structure (sometimes both).

This moves the tlb_flush call to the common reset function and
additionally ensures it is only done for the CONFIG_SOFTMMU case and
when tcg is enabled.

In some target cases we add an empty end_of_reset_fields structure to the
target vCPU structure so have a clear end point for any memset which
is resetting value in the structure before CPU_COMMON (where the TLB
structures are).

While this is a nice clean-up in general it is also a precursor for
changes coming to cputlb for MTTCG where the clearing of entries
can't be done arbitrarily across vCPUs. Currently the cpu_reset
function is usually called from the context of another vCPU as the
architectural power up sequence is run. By using the cputlb API
functions we can ensure the right behaviour in the future.

Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
Reviewed-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent b6c08970

qom/cpu.c

+4 −0
Original line number Diff line number Diff line
@@ -273,6 +273,10 @@ static void cpu_common_reset(CPUState *cpu) 
    for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {

        atomic_set(&cpu->tb_jmp_cache[i], NULL);

    }



#ifdef CONFIG_SOFTMMU

    tlb_flush(cpu, 0);

#endif

}



static bool cpu_common_has_work(CPUState *cs)

target/arm/cpu.c

+2 −3
Original line number Diff line number Diff line
@@ -122,7 +122,8 @@ static void arm_cpu_reset(CPUState *s) 


    acc->parent_reset(s);



    memset(env, 0, offsetof(CPUARMState, features));

    memset(env, 0, offsetof(CPUARMState, end_reset_fields));



    g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);

    g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
@@ -226,8 +227,6 @@ static void arm_cpu_reset(CPUState *s) 
                              &env->vfp.fp_status);

    set_float_detect_tininess(float_tininess_before_rounding,

                              &env->vfp.standard_fp_status);

    tlb_flush(s, 1);



#ifndef CONFIG_USER_ONLY

    if (kvm_enabled()) {

        kvm_arm_reset_vcpu(cpu);

target/arm/cpu.h

+4 −1
Original line number Diff line number Diff line
@@ -491,9 +491,12 @@ typedef struct CPUARMState { 
    struct CPUBreakpoint *cpu_breakpoint[16];

    struct CPUWatchpoint *cpu_watchpoint[16];



    /* Fields up to this point are cleared by a CPU reset */

    struct {} end_reset_fields;



    CPU_COMMON



    /* These fields after the common ones so they are preserved on reset.  */

    /* Fields after CPU_COMMON are preserved across CPU reset. */



    /* Internal CPU feature flags.  */

    uint64_t features;

target/cris/cpu.c

+1 −2
Original line number Diff line number Diff line
@@ -52,9 +52,8 @@ static void cris_cpu_reset(CPUState *s) 
    ccc->parent_reset(s);



    vr = env->pregs[PR_VR];

    memset(env, 0, offsetof(CPUCRISState, load_info));

    memset(env, 0, offsetof(CPUCRISState, end_reset_fields));

    env->pregs[PR_VR] = vr;

    tlb_flush(s, 1);



#if defined(CONFIG_USER_ONLY)

    /* start in user mode with interrupts enabled.  */

target/cris/cpu.h

+6 −3
Original line number Diff line number Diff line
@@ -167,6 +167,9 @@ typedef struct CPUCRISState { 
	 */

        TLBSet tlbsets[2][4][16];



        /* Fields up to this point are cleared by a CPU reset */

        struct {} end_reset_fields;



        CPU_COMMON



        /* Members from load_info on are preserved across resets.  */