Commit b6c08970 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2' into staging 



TriCore FPU patches

# gpg: Signature made Wed 11 Jan 2017 13:40:11 GMT
# gpg:                using RSA key 0x0AD2C6396B69CA14
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>"
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E  6E37 0AD2 C639 6B69 CA14

* remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2:
  target-tricore: Add updfl instruction
  target-tricore: Added new JNE instruction variant
  target-tricore: Added new MOV instruction variant
  target-tricore: Added MADD.F and MSUB.F instructions
  target-tricore: Added FTOUZ instruction

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 80fbc689 50788a3f

target/tricore/fpu_helper.c

+133 −1
Original line number Diff line number Diff line
@@ -21,7 +21,8 @@ 
#include "cpu.h"

#include "exec/helper-proto.h"



#define ADD_NAN   0x7cf00001

#define QUIET_NAN 0x7fc00000

#define ADD_NAN   0x7fc00001

#define DIV_NAN   0x7fc00008

#define MUL_NAN   0x7fc00002

#define FPU_FS PSW_USB_C
@@ -47,6 +48,42 @@ static inline bool f_is_denormal(float32 arg) 
    return float32_is_zero_or_denormal(arg) && !float32_is_zero(arg);

}



static inline float32 f_maddsub_nan_result(float32 arg1, float32 arg2,

                                           float32 arg3, float32 result,

                                           uint32_t muladd_negate_c)

{

    uint32_t aSign, bSign, cSign;

    uint32_t aExp, bExp, cExp;



    if (float32_is_any_nan(arg1) || float32_is_any_nan(arg2) ||

        float32_is_any_nan(arg3)) {

        return QUIET_NAN;

    } else if (float32_is_infinity(arg1) && float32_is_zero(arg2)) {

        return MUL_NAN;

    } else if (float32_is_zero(arg1) && float32_is_infinity(arg2)) {

        return MUL_NAN;

    } else {

        aSign = arg1 >> 31;

        bSign = arg2 >> 31;

        cSign = arg3 >> 31;



        aExp = (arg1 >> 23) & 0xff;

        bExp = (arg2 >> 23) & 0xff;

        cExp = (arg3 >> 23) & 0xff;



        if (muladd_negate_c) {

            cSign ^= 1;

        }

        if (((aExp == 0xff) || (bExp == 0xff)) && (cExp == 0xff)) {

            if (aSign ^ bSign ^ cSign) {

                return ADD_NAN;

            }

        }

    }



    return result;

}



static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)

{

    uint8_t some_excp = 0;
@@ -159,6 +196,60 @@ uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2) 
    return (uint32_t)f_result;

}



uint32_t helper_fmadd(CPUTriCoreState *env, uint32_t r1,

                      uint32_t r2, uint32_t r3)

{

    uint32_t flags;

    float32 arg1 = make_float32(r1);

    float32 arg2 = make_float32(r2);

    float32 arg3 = make_float32(r3);

    float32 f_result;



    f_result = float32_muladd(arg1, arg2, arg3, 0, &env->fp_status);



    flags = f_get_excp_flags(env);

    if (flags) {

        if (flags & float_flag_invalid) {

            arg1 = float32_squash_input_denormal(arg1, &env->fp_status);

            arg2 = float32_squash_input_denormal(arg2, &env->fp_status);

            arg3 = float32_squash_input_denormal(arg3, &env->fp_status);

            f_result = f_maddsub_nan_result(arg1, arg2, arg3, f_result, 0);

        }

        f_update_psw_flags(env, flags);

    } else {

        env->FPU_FS = 0;

    }

    return (uint32_t)f_result;

}



uint32_t helper_fmsub(CPUTriCoreState *env, uint32_t r1,

                      uint32_t r2, uint32_t r3)

{

    uint32_t flags;

    float32 arg1 = make_float32(r1);

    float32 arg2 = make_float32(r2);

    float32 arg3 = make_float32(r3);

    float32 f_result;



    f_result = float32_muladd(arg1, arg2, arg3, float_muladd_negate_product,

                              &env->fp_status);



    flags = f_get_excp_flags(env);

    if (flags) {

        if (flags & float_flag_invalid) {

            arg1 = float32_squash_input_denormal(arg1, &env->fp_status);

            arg2 = float32_squash_input_denormal(arg2, &env->fp_status);

            arg3 = float32_squash_input_denormal(arg3, &env->fp_status);



            f_result = f_maddsub_nan_result(arg1, arg2, arg3, f_result, 1);

        }

        f_update_psw_flags(env, flags);

    } else {

        env->FPU_FS = 0;

    }

    return (uint32_t)f_result;

}



uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1, uint32_t r2)

{

    uint32_t result, flags;
@@ -215,3 +306,44 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg) 
    }

    return (uint32_t)f_result;

}



uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)

{

    float32 f_arg = make_float32(arg);

    uint32_t result;

    int32_t flags;



    result = float32_to_uint32_round_to_zero(f_arg, &env->fp_status);



    flags = f_get_excp_flags(env);

    if (flags & float_flag_invalid) {

        flags &= ~float_flag_inexact;

        if (float32_is_any_nan(f_arg)) {

            result = 0;

        }

    } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {

        flags = float_flag_invalid;

        result = 0;

    }



    if (flags) {

        f_update_psw_flags(env, flags);

    } else {

        env->FPU_FS = 0;

    }

    return result;

}



void helper_updfl(CPUTriCoreState *env, uint32_t arg)

{

    env->FPU_FS =  extract32(arg, 7, 1) & extract32(arg, 15, 1);

    env->FPU_FI = (extract32(arg, 6, 1) & extract32(arg, 14, 1)) << 31;

    env->FPU_FV = (extract32(arg, 5, 1) & extract32(arg, 13, 1)) << 31;

    env->FPU_FZ = (extract32(arg, 4, 1) & extract32(arg, 12, 1)) << 31;

    env->FPU_FU = (extract32(arg, 3, 1) & extract32(arg, 11, 1)) << 31;

    /* clear FX and RM */

    env->PSW &= ~(extract32(arg, 10, 1) << 26);

    env->PSW |= (extract32(arg, 2, 1) & extract32(arg, 10, 1)) << 26;



    fpu_set_state(env);

}

target/tricore/helper.h

+4 −0
Original line number Diff line number Diff line
@@ -106,9 +106,13 @@ DEF_HELPER_3(fadd, i32, env, i32, i32) 
DEF_HELPER_3(fsub, i32, env, i32, i32)

DEF_HELPER_3(fmul, i32, env, i32, i32)

DEF_HELPER_3(fdiv, i32, env, i32, i32)

DEF_HELPER_4(fmadd, i32, env, i32, i32, i32)

DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)

DEF_HELPER_3(fcmp, i32, env, i32, i32)

DEF_HELPER_2(ftoi, i32, env, i32)

DEF_HELPER_2(itof, i32, env, i32)

DEF_HELPER_2(ftouz, i32, env, i32)

DEF_HELPER_2(updfl, void, env, i32)

/* dvinit */

DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)

DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)

target/tricore/translate.c

+48 −0
Original line number Diff line number Diff line
@@ -3362,9 +3362,17 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, 
    case OPC1_16_SBC_JEQ:

        gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);

        break;

    case OPC1_16_SBC_JEQ2:

        gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant,

                         offset + 16);

        break;

    case OPC1_16_SBC_JNE:

        gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);

        break;

    case OPC1_16_SBC_JNE2:

        gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15],

                         constant, offset + 16);

        break;

/* SBRN-format jumps */

    case OPC1_16_SBRN_JZ_T:

        temp = tcg_temp_new();
@@ -4097,6 +4105,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) 
        const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);

        gen_compute_branch(ctx, op1, 0, 0, const16, address);

        break;

    case OPC1_16_SBC_JEQ2:

    case OPC1_16_SBC_JNE2:

        if (tricore_feature(env, TRICORE_FEATURE_16)) {

            address = MASK_OP_SBC_DISP4(ctx->opcode);

            const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);

            gen_compute_branch(ctx, op1, 0, 0, const16, address);

        } else {

            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);

        }

        break;

/* SBRN-format */

    case OPC1_16_SBRN_JNZ_T:

    case OPC1_16_SBRN_JZ_T:
@@ -6034,6 +6052,8 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) 
    uint32_t op2;

    int r3, r2, r1;



    TCGv temp;



    r3 = MASK_OP_RR_D(ctx->opcode);

    r2 = MASK_OP_RR_S2(ctx->opcode);

    r1 = MASK_OP_RR_S1(ctx->opcode);
@@ -6224,6 +6244,20 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) 
    case OPC2_32_RR_MOV:

        tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);

        break;

    case OPC2_32_RR_MOV_64:

        if (tricore_feature(env, TRICORE_FEATURE_16)) {

            temp = tcg_temp_new();



            CHECK_REG_PAIR(r3);

            tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);

            tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);

            tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);



            tcg_temp_free(temp);

        } else {

            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);

        }

        break;

    case OPC2_32_RR_NE:

        tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],

                           cpu_gpr_d[r2]);
@@ -6699,6 +6733,12 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) 
    case OPC2_32_RR_ITOF:

        gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);

        break;

    case OPC2_32_RR_FTOUZ:

        gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);

        break;

    case OPC2_32_RR_UPDFL:

        gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);

        break;

    default:

        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);

    }
@@ -7094,6 +7134,14 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) 
    case OPC2_32_RRR_SUB_F:

        gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);

        break;

    case OPC2_32_RRR_MADD_F:

        gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],

                         cpu_gpr_d[r2], cpu_gpr_d[r3]);

        break;

    case OPC2_32_RRR_MSUB_F:

        gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],

                         cpu_gpr_d[r2], cpu_gpr_d[r3]);

        break;

    default:

        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);

    }

target/tricore/tricore-opcodes.h

+3 −0
Original line number Diff line number Diff line
@@ -311,6 +311,7 @@ enum { 
    OPC1_16_SRR_EQ                                   = 0x3a,

    OPC1_16_SB_J                                     = 0x3c,

    OPC1_16_SBC_JEQ                                  = 0x1e,

    OPC1_16_SBC_JEQ2                                 = 0x9e,

    OPC1_16_SBR_JEQ                                  = 0x3e,

    OPC1_16_SBR_JGEZ                                 = 0xce,

    OPC1_16_SBR_JGTZ                                 = 0x4e,
@@ -318,6 +319,7 @@ enum { 
    OPC1_16_SBR_JLEZ                                 = 0x8e,

    OPC1_16_SBR_JLTZ                                 = 0x0e,

    OPC1_16_SBC_JNE                                  = 0x5e,

    OPC1_16_SBC_JNE2                                 = 0xde,

    OPC1_16_SBR_JNE                                  = 0x7e,

    OPC1_16_SB_JNZ                                   = 0xee,

    OPC1_16_SBR_JNZ                                  = 0xf6,
@@ -1062,6 +1064,7 @@ enum { 
    OPC2_32_RR_MIN_H                             = 0x78,

    OPC2_32_RR_MIN_HU                            = 0x79,

    OPC2_32_RR_MOV                               = 0x1f,

    OPC2_32_RR_MOV_64                            = 0x81,

    OPC2_32_RR_NE                                = 0x11,

    OPC2_32_RR_OR_EQ                             = 0x27,

    OPC2_32_RR_OR_GE                             = 0x2b,