Commit 1ee91598 authored by Eduardo Habkost's avatar Eduardo Habkost
Browse files

Revert "target-i386: Disable HLE and RTM on Haswell & Broadwell" 



This reverts commit 13704e4c.

With the Intel microcode update that removed HLE and RTM, there will be
different kinds of Haswell and Broadwell CPUs out there: some that still
have the HLE and RTM features, and some that don't have the HLE and RTM
features. On both cases people may be willing to use the pc-*-2.3
machine-types.

So instead of making the CPU model results confusing by making it depend
on the machine-type, keep HLE and RTM on the existing Haswell and
Broadwell CPU models. The plan is to introduce "Haswell-noTSX" and
"Broadwell-noTSX" CPU models later, for people who have CPUs that don't
have TSX feature available.

Reviewed-by: default avatarDaniel P. Berrange <berrange@redhat.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent 3e5f6234

hw/i386/pc_piix.c

+0 −4
Original line number Diff line number Diff line
@@ -331,10 +331,6 @@ static void pc_compat_2_2(MachineState *machine) 
    x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);

    x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);

    x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);

    x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX,

                                CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);

    x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX,

                                CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);

    machine->suppress_vmdesc = true;

}

hw/i386/pc_q35.c

+0 −4
Original line number Diff line number Diff line
@@ -310,10 +310,6 @@ static void pc_compat_2_2(MachineState *machine) 
    x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);

    x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);

    x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);

    x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX,

                                CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);

    x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX,

                                CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);

    machine->suppress_vmdesc = true;

}

target-i386/cpu.c

+5 −4
Original line number Diff line number Diff line
@@ -1099,8 +1099,9 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT3_LAHF_LM,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |

            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |

            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,

            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |

            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |

            CPUID_7_0_EBX_RTM,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT,

        .xlevel = 0x8000000A,
@@ -1133,9 +1134,9 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |

            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |

            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |

            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |

            CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |

            CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |

            CPUID_7_0_EBX_SMAP,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT,