Commit 13704e4c authored by Eduardo Habkost's avatar Eduardo Habkost Committed by Paolo Bonzini
Browse files

target-i386: Disable HLE and RTM on Haswell & Broadwell 



All Haswell CPUs and some Broadwell CPUs were updated by Intel to have
the HLE and RTM features disabled. This will prevent
"-cpu Haswell,enforce" and "-cpu Broadwell,enforce" from running out of
the box on those CPUs.

Disable those features by default on Broadwell and Haswell CPU models,
starting on pc-*-2.3. Users who want to use those features can enable
them explicitly on the command-line.

Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 80fd48df

hw/i386/pc_piix.c

+4 −0
Original line number Diff line number Diff line
@@ -328,6 +328,10 @@ static void pc_compat_2_2(MachineState *machine) 
    x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);

    x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);

    x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);

    x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX,

                                CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);

    x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX,

                                CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);

}



static void pc_compat_2_1(MachineState *machine)

hw/i386/pc_q35.c

+4 −0
Original line number Diff line number Diff line
@@ -307,6 +307,10 @@ static void pc_compat_2_2(MachineState *machine) 
    x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);

    x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);

    x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);

    x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX,

                                CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);

    x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX,

                                CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);

}



static void pc_compat_2_1(MachineState *machine)

target-i386/cpu.c

+4 −5
Original line number Diff line number Diff line
@@ -1100,9 +1100,8 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT3_LAHF_LM,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |

            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |

            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |

            CPUID_7_0_EBX_RTM,

            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |

            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT,

        .xlevel = 0x8000000A,
@@ -1135,9 +1134,9 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |

            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |

            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |

            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |

            CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |

            CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |

            CPUID_7_0_EBX_SMAP,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT,