Commit 1edee470 authored Sep 14, 2015 by Edgar E. Iglesias Committed by Peter Maydell Sep 14, 2015

target-arm: Suppress TBI for S2 translations



Stage-2 MMU translations do not have configurable TBI as
the top byte is always 0 (48-bit IPAs).

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1442135278-25281-5-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

parent b698e9cf

target-arm/helper.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -6370,7 +6370,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
		if (arm_el_is_aa64(env, el)) {
		va_size = 64;
		if (el > 1) {
		if (mmu_idx != ARMMMUIdx_S2NS) {
		tbi = extract64(tcr->raw_tcr, 20, 1);
		}
		} else {
		if (extract64(address, 55, 1)) {
		tbi = extract64(tcr->raw_tcr, 38, 1);