Commit b698e9cf authored by Edgar E. Iglesias's avatar Edgar E. Iglesias Committed by Peter Maydell
Browse files

target-arm: Add VTTBR_EL2 



Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1442135278-25281-4-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 68e9c2fe

target-arm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -222,6 +222,7 @@ typedef struct CPUARMState { 
            };

            uint64_t ttbr1_el[4];

        };

        uint64_t vttbr_el2; /* Virtualization Translation Table Base.  */

        /* MMU translation table base control. */

        TCR tcr_el[4];

        TCR vtcr_el2; /* Virtualization Translation Control.  */

target-arm/helper.c

+32 −2
Original line number Diff line number Diff line
@@ -2213,6 +2213,20 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 
    raw_write(env, ri, value);

}



static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,

                        uint64_t value)

{

    ARMCPU *cpu = arm_env_get_cpu(env);

    CPUState *cs = CPU(cpu);



    /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */

    if (raw_read(env, ri) != value) {

        tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,

                            ARMMMUIdx_S2NS, -1);

        raw_write(env, ri, value);

    }

}



static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {

    { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,

      .access = PL1_RW, .type = ARM_CP_ALIAS,
@@ -3144,6 +3158,13 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { 
      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,

      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,

      .type = ARM_CP_CONST, .resetvalue = 0 },

    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,

      .cp = 15, .opc1 = 6, .crm = 2,

      .access = PL2_RW, .accessfn = access_el3_aa32ns,

      .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },

    { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,

      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },

    { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,

      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -3286,6 +3307,16 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { 
      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,

      .access = PL2_RW, .type = ARM_CP_ALIAS,

      .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },

    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,

      .cp = 15, .opc1 = 6, .crm = 2,

      .type = ARM_CP_64BIT | ARM_CP_ALIAS,

      .access = PL2_RW, .accessfn = access_el3_aa32ns,

      .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),

      .writefn = vttbr_write },

    { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,

      .access = PL2_RW, .writefn = vttbr_write,

      .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },

    { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,

      .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
@@ -5791,8 +5822,7 @@ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, 
                                   int ttbrn)

{

    if (mmu_idx == ARMMMUIdx_S2NS) {

        /* TODO: return VTTBR_EL2 */

        g_assert_not_reached();

        return env->cp15.vttbr_el2;

    }

    if (ttbrn == 0) {

        return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];