Unverified Commit 1e0d985f authored May 08, 2019 by Jonathan Behrens Committed by Palmer Dabbelt May 24, 2019

target/riscv: Only flush TLB if SATP.ASID changes

There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857



Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

parent 087b051a

target/riscv/csr.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -723,7 +723,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
		if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
		return -1;
		} else {
		if((val ^ env->satp) & SATP_ASID) {
		tlb_flush(CPU(riscv_env_get_cpu(env)));
		}
		env->satp = val;
		}
		}