Commit 1a136cdc authored by Ravi Bangoria's avatar Ravi Bangoria Committed by David Gibson
Browse files

target-ppc: Implement mtvsrws instruction 



mtvsrws: Move To VSR Word & Splat

Signed-off-by: default avatarRavi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: default avatarNikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 4879538c

target-ppc/translate/vsx-impl.inc.c

+19 −0
Original line number Diff line number Diff line
@@ -384,6 +384,25 @@ static void gen_mtvsrdd(DisasContext *ctx) 
    tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rB(ctx->opcode)]);

}



static void gen_mtvsrws(DisasContext *ctx)

{

    if (xT(ctx->opcode) < 32) {

        if (unlikely(!ctx->vsx_enabled)) {

            gen_exception(ctx, POWERPC_EXCP_VSXU);

            return;

        }

    } else {

        if (unlikely(!ctx->altivec_enabled)) {

            gen_exception(ctx, POWERPC_EXCP_VPU);

            return;

        }

    }



    tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)],

                        cpu_gpr[rA(ctx->opcode)], 32, 32);

    tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xT(ctx->opcode)));

}



#endif



static void gen_xxpermdi(DisasContext *ctx)

target-ppc/translate/vsx-ops.inc.c

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), 
GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),

GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),

GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),

GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),

#endif



#define GEN_XX1FORM(name, opc2, opc3, fl2)                              \