Commit 17552b97 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Convert VMOV (register) to decodetree

parent b8474540
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+10 −0
Original line number Diff line number Diff line
@@ -1889,6 +1889,16 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
    return true;
}

static bool trans_VMOV_reg_sp(DisasContext *s, arg_VMOV_reg_sp *a)
{
    return do_vfp_2op_sp(s, tcg_gen_mov_i32, a->vd, a->vm);
}

static bool trans_VMOV_reg_dp(DisasContext *s, arg_VMOV_reg_dp *a)
{
    return do_vfp_2op_dp(s, tcg_gen_mov_i64, a->vd, a->vm);
}

static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a)
{
    return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm);
+1 −7
Original line number Diff line number Diff line
@@ -3090,7 +3090,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                return 1;
            case 15:
                switch (rn) {
                case 1 ... 3:
                case 0 ... 3:
                    /* Already handled by decodetree */
                    return 1;
                default:
@@ -3103,9 +3103,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
            if (op == 15) {
                /* rn is opcode, encoded as per VFP_SREG_N. */
                switch (rn) {
                case 0x00: /* vmov */
                    break;

                case 0x04: /* vcvtb.f64.f16, vcvtb.f32.f16 */
                case 0x05: /* vcvtt.f64.f16, vcvtt.f32.f16 */
                    /*
@@ -3278,9 +3275,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                switch (op) {
                case 15: /* extension space */
                    switch (rn) {
                    case 0: /* cpy */
                        /* no-op */
                        break;
                    case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */
                    {
                        TCGv_ptr fpst = get_fpstatus_ptr(false);
+5 −0
Original line number Diff line number Diff line
@@ -157,6 +157,11 @@ VMOV_imm_sp ---- 1110 1.11 imm4h:4 .... 1010 0000 imm4l:4 \
VMOV_imm_dp  ---- 1110 1.11 imm4h:4 .... 1011 0000 imm4l:4 \
             vd=%vd_dp

VMOV_reg_sp  ---- 1110 1.11 0000 .... 1010 01.0 .... \
             vd=%vd_sp vm=%vm_sp
VMOV_reg_dp  ---- 1110 1.11 0000 .... 1011 01.0 .... \
             vd=%vd_dp vm=%vm_dp

VABS_sp      ---- 1110 1.11 0000 .... 1010 11.0 .... \
             vd=%vd_sp vm=%vm_sp
VABS_dp      ---- 1110 1.11 0000 .... 1011 11.0 .... \