Commit 166609e6 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-january-17-2019-v2' into staging 



MIPS queue for January 17, 2019 - v2

# gpg: Signature made Fri 18 Jan 2019 15:55:35 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-january-17-2019-v2:
  target/mips: Introduce 32 R5900 multimedia registers
  target/mips: Rename 'rn' to 'register_name'
  target/mips: Add CP0 register MemoryMapID
  target/mips: Amend preprocessor constants for CP0 registers
  target/mips: Update ITU to handle bus errors
  target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
  target/mips: Add field and R/W access to ITU control register ICR0
  target/mips: Provide R/W access to SAARI and SAAR CP0 registers
  target/mips: Add fields for SAARI and SAAR CP0 registers
  target/mips: Use preprocessor constants for 32 major CP0 registers
  target/mips: Add preprocessor constants for 32 major CP0 registers
  target/mips: Move comment containing summary of CP0 registers

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 5385a598 a168a796

hw/mips/cps.c

+8 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) 
    Error *err = NULL;

    target_ulong gcr_base;

    bool itu_present = false;

    bool saar_present = false;



    for (i = 0; i < s->num_vp; i++) {

        cpu = MIPS_CPU(cpu_create(s->cpu_type));
@@ -82,12 +83,14 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) 
            itu_present = true;

            /* Attach ITC Tag to the VP */

            env->itc_tag = mips_itu_get_tag_region(&s->itu);

            env->itu = &s->itu;

        }

        qemu_register_reset(main_cpu_reset, cpu);

    }



    cpu = MIPS_CPU(first_cpu);

    env = &cpu->env;

    saar_present = (bool)env->saarp;



    /* Inter-Thread Communication Unit */

    if (itu_present) {
@@ -96,6 +99,11 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) 


        object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);

        object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);

        object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",

                                 &err);

        if (saar_present) {

            qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR);

        }

        object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);

        if (err != NULL) {

            error_propagate(errp, err);

hw/misc/mips_itu.c

+66 −7
Original line number Diff line number Diff line
@@ -55,9 +55,17 @@ typedef enum ITCView { 
    ITCVIEW_EF_SYNC = 2,

    ITCVIEW_EF_TRY  = 3,

    ITCVIEW_PV_SYNC = 4,

    ITCVIEW_PV_TRY  = 5

    ITCVIEW_PV_TRY  = 5,

    ITCVIEW_PV_ICR0 = 15,

} ITCView;



#define ITC_ICR0_CELL_NUM        16

#define ITC_ICR0_BLK_GRAIN       8

#define ITC_ICR0_BLK_GRAIN_MASK  0x7

#define ITC_ICR0_ERR_AXI         2

#define ITC_ICR0_ERR_PARITY      1

#define ITC_ICR0_ERR_EXEC        0



MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)

{

    return &itu->tag_io;
@@ -76,7 +84,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size) 
    return tag->ITCAddressMap[index];

}



static void itc_reconfigure(MIPSITUState *tag)

void itc_reconfigure(MIPSITUState *tag)

{

    uint64_t *am = &tag->ITCAddressMap[0];

    MemoryRegion *mr = &tag->storage_io;
@@ -84,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag) 
    uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);

    bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;



    if (tag->saar_present) {

        address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4;

        size = 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f);

        is_enabled = *(uint64_t *) tag->saar & 1;

    }



    memory_region_transaction_begin();

    if (!(size & (size - 1))) {

        memory_region_set_size(mr, size);
@@ -142,8 +156,13 @@ static inline ITCView get_itc_view(hwaddr addr) 
static inline int get_cell_stride_shift(const MIPSITUState *s)

{

    /* Minimum interval (for EntryGain = 0) is 128 B */

    if (s->saar_present) {

        return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) &

                    ITC_ICR0_BLK_GRAIN_MASK);

    } else {

        return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);

    }

}



static inline ITCStorageCell *get_cell(MIPSITUState *s,

                                       hwaddr addr)
@@ -356,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c) 
    view_pv_common_write(c);

}



static void raise_exception(int excp)

{

    current_cpu->exception_index = excp;

    cpu_loop_exit(current_cpu);

}



static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)

{

    MIPSITUState *s = (MIPSITUState *)opaque;
@@ -363,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) 
    ITCView view = get_itc_view(addr);

    uint64_t ret = -1;



    switch (size) {

    case 1:

    case 2:

        s->icr0 |= 1 << ITC_ICR0_ERR_AXI;

        raise_exception(EXCP_DBE);

        return 0;

    }



    switch (view) {

    case ITCVIEW_BYPASS:

        ret = view_bypass_read(cell);
@@ -382,6 +415,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) 
    case ITCVIEW_PV_TRY:

        ret = view_pv_try_read(cell);

        break;

    case ITCVIEW_PV_ICR0:

        ret = s->icr0;

        break;

    default:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "itc_storage_read: Bad ITC View %d\n", (int)view);
@@ -398,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data, 
    ITCStorageCell *cell = get_cell(s, addr);

    ITCView view = get_itc_view(addr);



    switch (size) {

    case 1:

    case 2:

        s->icr0 |= 1 << ITC_ICR0_ERR_AXI;

        raise_exception(EXCP_DBE);

        return;

    }



    switch (view) {

    case ITCVIEW_BYPASS:

        view_bypass_write(cell, data);
@@ -417,6 +461,15 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data, 
    case ITCVIEW_PV_TRY:

        view_pv_try_write(cell);

        break;

    case ITCVIEW_PV_ICR0:

        if (data & 0x7) {

            /* clear ERROR bits */

            s->icr0 &= ~(data & 0x7);

        }

        /* set BLK_GRAIN */

        s->icr0 &= ~0x700;

        s->icr0 |= data & 0x700;

        break;

    default:

        qemu_log_mask(LOG_GUEST_ERROR,

                      "itc_storage_write: Bad ITC View %d\n", (int)view);
@@ -479,10 +532,15 @@ static void mips_itu_reset(DeviceState *dev) 
{

    MIPSITUState *s = MIPS_ITU(dev);



    if (s->saar_present) {

        *(uint64_t *) s->saar = 0x11 << 1;

        s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM;

    } else {

        s->ITCAddressMap[0] = 0;

        s->ITCAddressMap[1] =

            ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |

            (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);

    }

    itc_reconfigure(s);



    itc_reset_cells(s);
@@ -493,6 +551,7 @@ static Property mips_itu_properties[] = { 
                      ITC_FIFO_NUM_MAX),

    DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores,

                      ITC_SEMAPH_NUM_MAX),

    DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false),

    DEFINE_PROP_END_OF_LIST(),

};

include/hw/misc/mips_itu.h

+8 −0
Original line number Diff line number Diff line
@@ -66,6 +66,14 @@ typedef struct MIPSITUState { 
    /* ITC Configuration Tags */

    uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];

    MemoryRegion tag_io;



    /* ITU Control Register */

    uint64_t icr0;



    /* SAAR */

    bool saar_present;

    void *saar;



} MIPSITUState;



/* Get ITC Configuration Tag memory region. */

target/mips/cpu.h

+248 −83
Original line number Diff line number Diff line
@@ -123,87 +123,6 @@ typedef struct mips_def_t mips_def_t; 
#define MIPS_KSCRATCH_NUM 6

#define MIPS_MAAR_MAX 16 /* Must be an even number. */



typedef struct TCState TCState;

struct TCState {

    target_ulong gpr[32];

    target_ulong PC;

    target_ulong HI[MIPS_DSP_ACC];

    target_ulong LO[MIPS_DSP_ACC];

    target_ulong ACX[MIPS_DSP_ACC];

    target_ulong DSPControl;

    int32_t CP0_TCStatus;

#define CP0TCSt_TCU3	31

#define CP0TCSt_TCU2	30

#define CP0TCSt_TCU1	29

#define CP0TCSt_TCU0	28

#define CP0TCSt_TMX	27

#define CP0TCSt_RNST	23

#define CP0TCSt_TDS	21

#define CP0TCSt_DT	20

#define CP0TCSt_DA	15

#define CP0TCSt_A	13

#define CP0TCSt_TKSU	11

#define CP0TCSt_IXMT	10

#define CP0TCSt_TASID	0

    int32_t CP0_TCBind;

#define CP0TCBd_CurTC	21

#define CP0TCBd_TBE	17

#define CP0TCBd_CurVPE	0

    target_ulong CP0_TCHalt;

    target_ulong CP0_TCContext;

    target_ulong CP0_TCSchedule;

    target_ulong CP0_TCScheFBack;

    int32_t CP0_Debug_tcstatus;

    target_ulong CP0_UserLocal;



    int32_t msacsr;



#define MSACSR_FS       24

#define MSACSR_FS_MASK  (1 << MSACSR_FS)

#define MSACSR_NX       18

#define MSACSR_NX_MASK  (1 << MSACSR_NX)

#define MSACSR_CEF      2

#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)

#define MSACSR_RM       0

#define MSACSR_RM_MASK  (0x3 << MSACSR_RM)

#define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \

        MSACSR_FS_MASK)



    float_status msa_fp_status;



#define NUMBER_OF_MXU_REGISTERS 16

    target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];

    target_ulong mxu_cr;

#define MXU_CR_LC       31

#define MXU_CR_RC       30

#define MXU_CR_BIAS     2

#define MXU_CR_RD_EN    1

#define MXU_CR_MXU_EN   0



};



typedef struct CPUMIPSState CPUMIPSState;

struct CPUMIPSState {

    TCState active_tc;

    CPUMIPSFPUContext active_fpu;



    uint32_t current_tc;

    uint32_t current_fpu;



    uint32_t SEGBITS;

    uint32_t PABITS;

#if defined(TARGET_MIPS64)

# define PABITS_BASE 36

#else

# define PABITS_BASE 32

#endif

    target_ulong SEGMask;

    uint64_t PAMask;

#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)



    int32_t msair;

#define MSAIR_ProcID    8

#define MSAIR_Rev       0



/*

 *     Summary of CP0 registers
@@ -245,8 +164,8 @@ struct CPUMIPSState { 
 * 3   BadInstrX

 * 4                                       GuestCtl1         GuestCtl0Ext

 * 5                                       GuestCtl2

 * 6                                       GuestCtl3

 * 7

 * 6                     SAARI             GuestCtl3

 * 7                     SAAR

 *

 *

 *     Register 12       Register 13       Register 14       Register 15
@@ -314,6 +233,240 @@ struct CPUMIPSState { 
 * 7   TagLo             TagHi                               KScratch<n>

 *

 */

#define CP0_REGISTER_00     0

#define CP0_REGISTER_01     1

#define CP0_REGISTER_02     2

#define CP0_REGISTER_03     3

#define CP0_REGISTER_04     4

#define CP0_REGISTER_05     5

#define CP0_REGISTER_06     6

#define CP0_REGISTER_07     7

#define CP0_REGISTER_08     8

#define CP0_REGISTER_09     9

#define CP0_REGISTER_10    10

#define CP0_REGISTER_11    11

#define CP0_REGISTER_12    12

#define CP0_REGISTER_13    13

#define CP0_REGISTER_14    14

#define CP0_REGISTER_15    15

#define CP0_REGISTER_16    16

#define CP0_REGISTER_17    17

#define CP0_REGISTER_18    18

#define CP0_REGISTER_19    19

#define CP0_REGISTER_20    20

#define CP0_REGISTER_21    21

#define CP0_REGISTER_22    22

#define CP0_REGISTER_23    23

#define CP0_REGISTER_24    24

#define CP0_REGISTER_25    25

#define CP0_REGISTER_26    26

#define CP0_REGISTER_27    27

#define CP0_REGISTER_28    28

#define CP0_REGISTER_29    29

#define CP0_REGISTER_30    30

#define CP0_REGISTER_31    31





/* CP0 Register 00 */

#define CP0_REG00__INDEX           0

#define CP0_REG00__VPCONTROL       4

/* CP0 Register 01 */

/* CP0 Register 02 */

#define CP0_REG02__ENTRYLO0        0

/* CP0 Register 03 */

#define CP0_REG03__ENTRYLO1        0

#define CP0_REG03__GLOBALNUM       1

/* CP0 Register 04 */

#define CP0_REG04__CONTEXT         0

#define CP0_REG04__USERLOCAL       2

#define CP0_REG04__DBGCONTEXTID    4

#define CP0_REG00__MMID            5

/* CP0 Register 05 */

#define CP0_REG05__PAGEMASK        0

#define CP0_REG05__PAGEGRAIN       1

/* CP0 Register 06 */

#define CP0_REG06__WIRED           0

/* CP0 Register 07 */

#define CP0_REG07__HWRENA          0

/* CP0 Register 08 */

#define CP0_REG08__BADVADDR        0

#define CP0_REG08__BADINSTR        1

#define CP0_REG08__BADINSTRP       2

/* CP0 Register 09 */

#define CP0_REG09__COUNT           0

#define CP0_REG09__SAARI           6

#define CP0_REG09__SAAR            7

/* CP0 Register 10 */

#define CP0_REG10__ENTRYHI         0

#define CP0_REG10__GUESTCTL1       4

#define CP0_REG10__GUESTCTL2       5

/* CP0 Register 11 */

#define CP0_REG11__COMPARE         0

#define CP0_REG11__GUESTCTL0EXT    4

/* CP0 Register 12 */

#define CP0_REG12__STATUS          0

#define CP0_REG12__INTCTL          1

#define CP0_REG12__SRSCTL          2

#define CP0_REG12__GUESTCTL0       6

#define CP0_REG12__GTOFFSET        7

/* CP0 Register 13 */

#define CP0_REG13__CAUSE           0

/* CP0 Register 14 */

#define CP0_REG14__EPC             0

/* CP0 Register 15 */

#define CP0_REG15__PRID            0

#define CP0_REG15__EBASE           1

#define CP0_REG15__CDMMBASE        2

#define CP0_REG15__CMGCRBASE       3

/* CP0 Register 16 */

#define CP0_REG16__CONFIG          0

#define CP0_REG16__CONFIG1         1

#define CP0_REG16__CONFIG2         2

#define CP0_REG16__CONFIG3         3

#define CP0_REG16__CONFIG4         4

#define CP0_REG16__CONFIG5         5

#define CP0_REG00__CONFIG7         7

/* CP0 Register 17 */

#define CP0_REG17__LLADDR          0

#define CP0_REG17__MAAR            1

#define CP0_REG17__MAARI           2

/* CP0 Register 18 */

#define CP0_REG18__WATCHLO0        0

#define CP0_REG18__WATCHLO1        1

#define CP0_REG18__WATCHLO2        2

#define CP0_REG18__WATCHLO3        3

/* CP0 Register 19 */

#define CP0_REG19__WATCHHI0        0

#define CP0_REG19__WATCHHI1        1

#define CP0_REG19__WATCHHI2        2

#define CP0_REG19__WATCHHI3        3

/* CP0 Register 20 */

#define CP0_REG20__XCONTEXT        0

/* CP0 Register 21 */

/* CP0 Register 22 */

/* CP0 Register 23 */

#define CP0_REG23__DEBUG           0

/* CP0 Register 24 */

#define CP0_REG24__DEPC            0

/* CP0 Register 25 */

#define CP0_REG25__PERFCTL0        0

#define CP0_REG25__PERFCNT0        1

#define CP0_REG25__PERFCTL1        2

#define CP0_REG25__PERFCNT1        3

#define CP0_REG25__PERFCTL2        4

#define CP0_REG25__PERFCNT2        5

#define CP0_REG25__PERFCTL3        6

#define CP0_REG25__PERFCNT3        7

/* CP0 Register 26 */

#define CP0_REG00__ERRCTL          0

/* CP0 Register 27 */

#define CP0_REG27__CACHERR         0

/* CP0 Register 28 */

#define CP0_REG28__ITAGLO          0

#define CP0_REG28__IDATALO         1

#define CP0_REG28__DTAGLO          2

#define CP0_REG28__DDATALO         3

/* CP0 Register 29 */

#define CP0_REG29__IDATAHI         1

#define CP0_REG29__DDATAHI         3

/* CP0 Register 30 */

#define CP0_REG30__ERROREPC        0

/* CP0 Register 31 */

#define CP0_REG31__DESAVE          0

#define CP0_REG31__KSCRATCH1       2

#define CP0_REG31__KSCRATCH2       3

#define CP0_REG31__KSCRATCH3       4

#define CP0_REG31__KSCRATCH4       5

#define CP0_REG31__KSCRATCH5       6

#define CP0_REG31__KSCRATCH6       7





typedef struct TCState TCState;

struct TCState {

    target_ulong gpr[32];

    target_ulong PC;

    target_ulong HI[MIPS_DSP_ACC];

    target_ulong LO[MIPS_DSP_ACC];

    target_ulong ACX[MIPS_DSP_ACC];

    target_ulong DSPControl;

    int32_t CP0_TCStatus;

#define CP0TCSt_TCU3    31

#define CP0TCSt_TCU2    30

#define CP0TCSt_TCU1    29

#define CP0TCSt_TCU0    28

#define CP0TCSt_TMX     27

#define CP0TCSt_RNST    23

#define CP0TCSt_TDS     21

#define CP0TCSt_DT      20

#define CP0TCSt_DA      15

#define CP0TCSt_A       13

#define CP0TCSt_TKSU    11

#define CP0TCSt_IXMT    10

#define CP0TCSt_TASID   0

    int32_t CP0_TCBind;

#define CP0TCBd_CurTC   21

#define CP0TCBd_TBE     17

#define CP0TCBd_CurVPE  0

    target_ulong CP0_TCHalt;

    target_ulong CP0_TCContext;

    target_ulong CP0_TCSchedule;

    target_ulong CP0_TCScheFBack;

    int32_t CP0_Debug_tcstatus;

    target_ulong CP0_UserLocal;



    int32_t msacsr;



#define MSACSR_FS       24

#define MSACSR_FS_MASK  (1 << MSACSR_FS)

#define MSACSR_NX       18

#define MSACSR_NX_MASK  (1 << MSACSR_NX)

#define MSACSR_CEF      2

#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)

#define MSACSR_RM       0

#define MSACSR_RM_MASK  (0x3 << MSACSR_RM)

#define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \

        MSACSR_FS_MASK)



    float_status msa_fp_status;



    /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */

    uint64_t mmr[32];



#define NUMBER_OF_MXU_REGISTERS 16

    target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];

    target_ulong mxu_cr;

#define MXU_CR_LC       31

#define MXU_CR_RC       30

#define MXU_CR_BIAS     2

#define MXU_CR_RD_EN    1

#define MXU_CR_MXU_EN   0



};



struct MIPSITUState;

typedef struct CPUMIPSState CPUMIPSState;

struct CPUMIPSState {

    TCState active_tc;

    CPUMIPSFPUContext active_fpu;



    uint32_t current_tc;

    uint32_t current_fpu;



    uint32_t SEGBITS;

    uint32_t PABITS;

#if defined(TARGET_MIPS64)

# define PABITS_BASE 36

#else

# define PABITS_BASE 32

#endif

    target_ulong SEGMask;

    uint64_t PAMask;

#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)



    int32_t msair;

#define MSAIR_ProcID    8

#define MSAIR_Rev       0



/*

 * CP0 Register 0

 */
@@ -386,6 +539,7 @@ struct CPUMIPSState { 
 */

    target_ulong CP0_Context;

    target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];

    int32_t CP0_MemoryMapID;

/*

 * CP0 Register 5

 */
@@ -511,6 +665,12 @@ struct CPUMIPSState { 
 * CP0 Register 9

 */

    int32_t CP0_Count;

    uint32_t CP0_SAARI;

#define CP0SAARI_TARGET 0    /*  5..0  */

    uint64_t CP0_SAAR[2];

#define CP0SAAR_BASE    12   /* 43..12 */

#define CP0SAAR_SIZE    1    /*  5..1  */

#define CP0SAAR_EN      0

/*

 * CP0 Register 10

 */
@@ -860,6 +1020,7 @@ struct CPUMIPSState { 
    uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */

    uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */

    uint64_t insn_flags; /* Supported instruction set */

    int saarp;



    /* Fields up to this point are cleared by a CPU reset */

    struct {} end_reset_fields;
@@ -875,6 +1036,7 @@ struct CPUMIPSState { 
    const mips_def_t *cpu_model;

    void *irq[8];

    QEMUTimer *timer; /* Internal timer */

    struct MIPSITUState *itu;

    MemoryRegion *itc_tag; /* ITC Configuration Tags */

    target_ulong exception_base; /* ExceptionBase input to the core */

};
@@ -1017,6 +1179,9 @@ void cpu_set_exception_base(int vp_index, target_ulong address); 
/* mips_int.c */

void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);



/* mips_itu.c */

void itc_reconfigure(struct MIPSITUState *tag);



/* helper.c */

target_ulong exception_resume_pc (CPUMIPSState *env);

target/mips/helper.h

+6 −0
Original line number Diff line number Diff line
@@ -65,6 +65,8 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env) 
DEF_HELPER_1(mfc0_tcschefback, tl, env)

DEF_HELPER_1(mftc0_tcschefback, tl, env)

DEF_HELPER_1(mfc0_count, tl, env)

DEF_HELPER_1(mfc0_saar, tl, env)

DEF_HELPER_1(mfhc0_saar, tl, env)

DEF_HELPER_1(mftc0_entryhi, tl, env)

DEF_HELPER_1(mftc0_status, tl, env)

DEF_HELPER_1(mftc0_cause, tl, env)
@@ -87,6 +89,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env) 
DEF_HELPER_1(dmfc0_lladdr, tl, env)

DEF_HELPER_1(dmfc0_maar, tl, env)

DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)

DEF_HELPER_1(dmfc0_saar, tl, env)

#endif /* TARGET_MIPS64 */



DEF_HELPER_2(mtc0_index, void, env, tl)
@@ -131,6 +134,9 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl) 
DEF_HELPER_2(mtc0_hwrena, void, env, tl)

DEF_HELPER_2(mtc0_pwctl, void, env, tl)

DEF_HELPER_2(mtc0_count, void, env, tl)

DEF_HELPER_2(mtc0_saari, void, env, tl)

DEF_HELPER_2(mtc0_saar, void, env, tl)

DEF_HELPER_2(mthc0_saar, void, env, tl)

DEF_HELPER_2(mtc0_entryhi, void, env, tl)

DEF_HELPER_2(mttc0_entryhi, void, env, tl)

DEF_HELPER_2(mtc0_compare, void, env, tl)