Commit a168a796 authored by Fredrik Noring's avatar Fredrik Noring Committed by Aleksandar Markovic
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target/mips: Introduce 32 R5900 multimedia registers 



The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.

Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarFredrik Noring <noring@nocrew.org>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 294fc2ea

target/mips/cpu.h

+3 −0
Original line number Diff line number Diff line
@@ -429,6 +429,9 @@ struct TCState { 


    float_status msa_fp_status;



    /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */

    uint64_t mmr[32];



#define NUMBER_OF_MXU_REGISTERS 16

    target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];

    target_ulong mxu_cr;

target/mips/translate.c

+16 −0
Original line number Diff line number Diff line
@@ -2455,6 +2455,11 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; 
static TCGv_i64 fpu_f64[32];

static TCGv_i64 msa_wr_d[64];









#if defined(TARGET_MIPS64)









/* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) */









static TCGv_i64 cpu_mmr[32];









#endif

















#if !defined(TARGET_MIPS64)









/* MXU registers */









static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];








@@ -29845,6 +29850,17 @@ void mips_tcg_init(void)







    fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,









                                       offsetof(CPUMIPSState, active_fpu.fcr31),









                                       "fcr31");

















#if defined(TARGET_MIPS64)









    cpu_mmr[0] = NULL;









    for (i = 1; i < 32; i++) {









        cpu_mmr[i] = tcg_global_mem_new_i64(cpu_env,









                                            offsetof(CPUMIPSState,









                                                     active_tc.mmr[i]),









                                            regnames[i]);









    }









#endif

















#if !defined(TARGET_MIPS64)









    for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {









        mxu_gpr[i] = tcg_global_mem_new(cpu_env,