Unverified Commit 14115b91 authored Aug 23, 2019 by Alistair Francis Committed by Palmer Dabbelt Sep 17, 2019

target/riscv: Fix mstatus dirty mask



This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.

Fixes: 1f0419cb ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

parent a9f37afa

target/riscv/csr.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -335,7 +335,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
		* RV32: MPV and MTL are not in mstatus. The current plan is to
		* add them to mstatush. For now, we just don't support it.
		*/
		mask \|= MSTATUS_MPP \| MSTATUS_MPV;
		mask \|= MSTATUS_MTL \| MSTATUS_MPV;
		#endif
		}