Unverified Commit a9f37afa authored by Atish Patra's avatar Atish Patra Committed by Palmer Dabbelt
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target/riscv: Use both register name and ABI name 



Use both the generic register name and ABI name for the general purpose
registers and floating point registers.

Signed-off-by: default avatarAtish Patra <atish.patra@wdc.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarBin Meng <bmeng.cn@gmail.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent d372e748

target/riscv/cpu.c

+11 −8
Original line number Diff line number Diff line
@@ -34,17 +34,20 @@ 
static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";



const char * const riscv_int_regnames[] = {

  "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2",

  "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5",

  "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7",

  "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6"

  "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",

  "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",

  "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",

  "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",

  "x28/t3",  "x29/t4", "x30/t5", "x31/t6"

};



const char * const riscv_fpr_regnames[] = {

  "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",

  "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",

  "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",

  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"

  "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",

  "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",

  "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",

  "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",

  "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",

  "f30/ft10", "f31/ft11"

};



const char * const riscv_excp_names[] = {