Commit 0c591eb0 authored by Andreas Färber's avatar Andreas Färber
Browse files

cputlb: Change tlb_set_page() argument to CPUState 



Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent 00c8cb0a

cputlb.c

+2 −2
Original line number Diff line number Diff line
@@ -221,10 +221,11 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, 
/* Add a new TLB entry. At most one entry for a given virtual address

   is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the

   supplied size is only used by tlb_flush_page.  */

void tlb_set_page(CPUArchState *env, target_ulong vaddr,

void tlb_set_page(CPUState *cpu, target_ulong vaddr,

                  hwaddr paddr, int prot,

                  int mmu_idx, target_ulong size)

{

    CPUArchState *env = cpu->env_ptr;

    MemoryRegionSection *section;

    unsigned int index;

    target_ulong address;
@@ -232,7 +233,6 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, 
    uintptr_t addend;

    CPUTLBEntry *te;

    hwaddr iotlb, xlat, sz;

    CPUState *cpu = ENV_GET_CPU(env);



    assert(size >= TARGET_PAGE_SIZE);

    if (size != TARGET_PAGE_SIZE) {

include/exec/exec-all.h

+1 −1
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); 
/* cputlb.c */

void tlb_flush_page(CPUState *cpu, target_ulong addr);

void tlb_flush(CPUState *cpu, int flush_global);

void tlb_set_page(CPUArchState *env, target_ulong vaddr,

void tlb_set_page(CPUState *cpu, target_ulong vaddr,

                  hwaddr paddr, int prot,

                  int mmu_idx, target_ulong size);

void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);

target-alpha/helper.c

+1 −1
Original line number Diff line number Diff line
@@ -345,7 +345,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw, 
        return 1;

    }



    tlb_set_page(env, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,

    tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,

                 prot, mmu_idx, TARGET_PAGE_SIZE);

    return 0;

}

target-arm/helper.c

+1 −1
Original line number Diff line number Diff line
@@ -3676,7 +3676,7 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, 
        /* Map a single [sub]page.  */

        phys_addr &= ~(hwaddr)0x3ff;

        address &= ~(uint32_t)0x3ff;

        tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);

        tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);

        return 0;

    }

target-cris/helper.c

+1 −1
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 
         */

        phy = res.phy & ~0x80000000;

        prot = res.prot;

        tlb_set_page(env, address & TARGET_PAGE_MASK, phy,

        tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,

                     prot, mmu_idx, TARGET_PAGE_SIZE);

        r = 0;

    }