Commit 00c8cb0a authored by Andreas Färber's avatar Andreas Färber
Browse files

cputlb: Change tlb_flush() argument to CPUState 



Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent 31b030d4

cputlb.c

+3 −3
Original line number Diff line number Diff line
@@ -46,9 +46,9 @@ int tlb_flush_count; 
 * entries from the TLB at any time, so flushing more entries than

 * required is only an efficiency issue, not a correctness issue.

 */

void tlb_flush(CPUArchState *env, int flush_global)

void tlb_flush(CPUState *cpu, int flush_global)

{

    CPUState *cpu = ENV_GET_CPU(env);

    CPUArchState *env = cpu->env_ptr;



#if defined(DEBUG_TLB)

    printf("tlb_flush:\n");
@@ -93,7 +93,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) 
               TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",

               env->tlb_flush_addr, env->tlb_flush_mask);

#endif

        tlb_flush(env, 1);

        tlb_flush(cpu, 1);

        return;

    }

    /* must reset current TB so that interrupts cannot modify the

exec.c

+1 −3
Original line number Diff line number Diff line
@@ -1834,14 +1834,12 @@ static void tcg_commit(MemoryListener *listener) 
       reset the modified entries */

    /* XXX: slow ! */

    CPU_FOREACH(cpu) {

        CPUArchState *env = cpu->env_ptr;



        /* FIXME: Disentangle the cpu.h circular files deps so we can

           directly get the right CPU from listener.  */

        if (cpu->tcg_as_listener != listener) {

            continue;

        }

        tlb_flush(env, 1);

        tlb_flush(cpu, 1);

    }

}

hw/sh4/sh7750.c

+1 −1
Original line number Diff line number Diff line
@@ -416,7 +416,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr, 
    case SH7750_PTEH_A7:

        /* If asid changes, clear all registered tlb entries. */

        if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {

            tlb_flush(&s->cpu->env, 1);

            tlb_flush(CPU(s->cpu), 1);

        }

        s->cpu->env.pteh = mem_value;

        return;

include/exec/exec-all.h

+2 −2
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, 
void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);

/* cputlb.c */

void tlb_flush_page(CPUState *cpu, target_ulong addr);

void tlb_flush(CPUArchState *env, int flush_global);

void tlb_flush(CPUState *cpu, int flush_global);

void tlb_set_page(CPUArchState *env, target_ulong vaddr,

                  hwaddr paddr, int prot,

                  int mmu_idx, target_ulong size);
@@ -109,7 +109,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) 
{

}



static inline void tlb_flush(CPUArchState *env, int flush_global)

static inline void tlb_flush(CPUState *cpu, int flush_global)

{

}

#endif

target-alpha/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -258,7 +258,7 @@ static void alpha_cpu_initfn(Object *obj) 


    cs->env_ptr = env;

    cpu_exec_init(env);

    tlb_flush(env, 1);

    tlb_flush(cs, 1);



    alpha_translate_init();