Commit 31b030d4 authored by Andreas Färber's avatar Andreas Färber
Browse files

cputlb: Change tlb_flush_page() argument to CPUState 



Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent 0063ebd6

cputlb.c

+2 −2
Original line number Diff line number Diff line
@@ -77,9 +77,9 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) 
    }

}



void tlb_flush_page(CPUArchState *env, target_ulong addr)

void tlb_flush_page(CPUState *cpu, target_ulong addr)

{

    CPUState *cpu = ENV_GET_CPU(env);

    CPUArchState *env = cpu->env_ptr;

    int i;

    int mmu_idx;

exec.c

+2 −5
Original line number Diff line number Diff line
@@ -543,7 +543,6 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, 
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,

                          int flags, CPUWatchpoint **watchpoint)

{

    CPUArchState *env = cpu->env_ptr;

    vaddr len_mask = ~(len - 1);

    CPUWatchpoint *wp;
@@ -567,7 +566,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, 
        QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);

    }



    tlb_flush_page(env, addr);

    tlb_flush_page(cpu, addr);



    if (watchpoint)

        *watchpoint = wp;
@@ -594,11 +593,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, 
/* Remove a specific watchpoint by reference.  */

void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)

{

    CPUArchState *env = cpu->env_ptr;



    QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);



    tlb_flush_page(env, watchpoint->vaddr);

    tlb_flush_page(cpu, watchpoint->vaddr);



    g_free(watchpoint);

}

include/exec/exec-all.h

+2 −2
Original line number Diff line number Diff line
@@ -98,14 +98,14 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, 
#if !defined(CONFIG_USER_ONLY)

void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);

/* cputlb.c */

void tlb_flush_page(CPUArchState *env, target_ulong addr);

void tlb_flush_page(CPUState *cpu, target_ulong addr);

void tlb_flush(CPUArchState *env, int flush_global);

void tlb_set_page(CPUArchState *env, target_ulong vaddr,

                  hwaddr paddr, int prot,

                  int mmu_idx, target_ulong size);

void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);

#else

static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)

static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)

{

}

target-alpha/sys_helper.c

+1 −1
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ void helper_tbia(CPUAlphaState *env) 


void helper_tbis(CPUAlphaState *env, uint64_t p)

{

    tlb_flush_page(env, p);

    tlb_flush_page(CPU(alpha_env_get_cpu(env)), p);

}



void helper_tb_flush(CPUAlphaState *env)

target-arm/helper.c

+10 −4
Original line number Diff line number Diff line
@@ -342,7 +342,9 @@ static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, 
                          uint64_t value)

{

    /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */

    tlb_flush_page(env, value & TARGET_PAGE_MASK);

    ARMCPU *cpu = arm_env_get_cpu(env);



    tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);

}



static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -356,7 +358,9 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, 
                           uint64_t value)

{

    /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */

    tlb_flush_page(env, value & TARGET_PAGE_MASK);

    ARMCPU *cpu = arm_env_get_cpu(env);



    tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);

}



static const ARMCPRegInfo cp_reginfo[] = {
@@ -1686,16 +1690,18 @@ static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, 
                               uint64_t value)

{

    /* Invalidate by VA (AArch64 version) */

    ARMCPU *cpu = arm_env_get_cpu(env);

    uint64_t pageaddr = value << 12;

    tlb_flush_page(env, pageaddr);

    tlb_flush_page(CPU(cpu), pageaddr);

}



static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,

                                uint64_t value)

{

    /* Invalidate by VA, all ASIDs (AArch64 version) */

    ARMCPU *cpu = arm_env_get_cpu(env);

    uint64_t pageaddr = value << 12;

    tlb_flush_page(env, pageaddr);

    tlb_flush_page(CPU(cpu), pageaddr);

}



static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,