Commit 0bc472a9 authored by Kuo-Jung Su's avatar Kuo-Jung Su Committed by Edgar E. Iglesias
Browse files

hw/nand.c: correct the sense of the BUSY/READY status bit 

The BIT6 of Status Register(SR):

SR[6] behaves the same as R/B# pin
    SR[6] = 0 indicates the device is busy;
    SR[6] = 1 means the device is ready

Some NAND flash controller (i.e. ftnandc021) relies on the SR[6]
to determine if the NAND flash erase/program is success or error timeout.

P.S:
The exmaple NAND flash datasheet could be found at following link:
http://www.mxic.com.tw/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/8FEA549237D2F7674825795800104C26/$File/MX30LF1G08AA,%203V,%201Gb,%20v1.1.pdf



Signed-off-by: default avatarKuo-Jung Su <dantesu@gmail.com>
Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@gmail.com>
parent 76c48503

hw/nand.c

+2 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ 
# define NAND_IOSTATUS_PLANE1	(1 << 2)

# define NAND_IOSTATUS_PLANE2	(1 << 3)

# define NAND_IOSTATUS_PLANE3	(1 << 4)

# define NAND_IOSTATUS_BUSY	(1 << 6)

# define NAND_IOSTATUS_READY    (1 << 6)

# define NAND_IOSTATUS_UNPROTCT	(1 << 7)



# define MAX_PAGE		0x800
@@ -231,6 +231,7 @@ static void nand_reset(DeviceState *dev) 
    s->iolen = 0;

    s->offset = 0;

    s->status &= NAND_IOSTATUS_UNPROTCT;

    s->status |= NAND_IOSTATUS_READY;

}



static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)