Commit 76c48503 authored by Aurelien Jarno's avatar Aurelien Jarno
Browse files

Merge branch 'target-arm.next' of git://git.linaro.org/people/pmaydell/qemu-arm 

* 'target-arm.next' of git://git.linaro.org/people/pmaydell/qemu-arm:
  MAINTAINERS: add entry for ARM KVM guest cores
  configure: Enable KVM on ARM
  hw/kvm/arm_gic: Implement support for KVM in-kernel ARM GIC
  target-arm: Use MemoryListener to identify GIC base address for KVM
  hw/arm_gic: Convert ARM GIC classes to use init/realize
  hw/arm_gic: Add presave/postload hooks
  ARM KVM: save and load VFP registers from kernel
  ARM: KVM: Add support for KVM on ARM architecture
  target-arm: Drop CPUARMState* argument from bank_number()
  linux-headers: resync from mainline to add ARM KVM headers
  oslib-posix: Align to permit transparent hugepages on ARM Linux
  target-arm: Don't decode RFE or SRS on M profile cores
  target-arm: Factor out handling of SRS instruction
parents 597e2cec ed4659d1

MAINTAINERS

+5 −0
Original line number Diff line number Diff line
@@ -140,6 +140,11 @@ S: Supported 
F: kvm-*

F: */kvm.*



ARM

M: Peter Maydell <peter.maydell@linaro.org>

S: Maintained

F: target-arm/kvm.c



PPC

M: Alexander Graf <agraf@suse.de>

S: Maintained

configure

+1 −1
Original line number Diff line number Diff line
@@ -4134,7 +4134,7 @@ case "$target_arch2" in 
    echo "CONFIG_NO_XEN=y" >> $config_target_mak

esac

case "$target_arch2" in

  i386|x86_64|ppcemb|ppc|ppc64|s390x)

  arm|i386|x86_64|ppcemb|ppc|ppc64|s390x)

    # Make sure the target and host cpus are compatible

    if test "$kvm" = "yes" -a "$target_softmmu" = "yes" -a \

      \( "$target_arch2" = "$cpu" -o \

hw/a15mpcore.c

+7 −1
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
 */



#include "sysbus.h"

#include "sysemu/kvm.h"



/* A15MP private memory region.  */
@@ -40,8 +41,13 @@ static int a15mp_priv_init(SysBusDevice *dev) 
{

    A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev);

    SysBusDevice *busdev;

    const char *gictype = "arm_gic";



    s->gic = qdev_create(NULL, "arm_gic");

    if (kvm_irqchip_in_kernel()) {

        gictype = "kvm-arm-gic";

    }



    s->gic = qdev_create(NULL, gictype);

    qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);

    qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);

    qdev_prop_set_uint32(s->gic, "revision", 2);

hw/arm/Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -32,5 +32,6 @@ obj-y += collie.o 
obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o

obj-y += kzm.o

obj-$(CONFIG_FDT) += ../device_tree.o

obj-$(CONFIG_KVM) += kvm/arm_gic.o



obj-y := $(addprefix ../,$(obj-y))

hw/arm_gic.c

+13 −10
Original line number Diff line number Diff line
@@ -659,14 +659,18 @@ void gic_init_irqs_and_distributor(GICState *s, int num_irq) 
    memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);

}



static int arm_gic_init(SysBusDevice *dev)

static void arm_gic_realize(DeviceState *dev, Error **errp)

{

    /* Device instance init function for the GIC sysbus device */

    /* Device instance realize function for the GIC sysbus device */

    int i;

    GICState *s = FROM_SYSBUS(GICState, dev);

    GICState *s = ARM_GIC(dev);

    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

    ARMGICClass *agc = ARM_GIC_GET_CLASS(s);



    agc->parent_init(dev);

    agc->parent_realize(dev, errp);

    if (error_is_set(errp)) {

        return;

    }



    gic_init_irqs_and_distributor(s, s->num_irq);
@@ -686,22 +690,21 @@ static int arm_gic_init(SysBusDevice *dev) 
                              "gic_cpu", 0x100);

    }

    /* Distributor */

    sysbus_init_mmio(dev, &s->iomem);

    sysbus_init_mmio(sbd, &s->iomem);

    /* cpu interfaces (one for "current cpu" plus one per cpu) */

    for (i = 0; i <= NUM_CPU(s); i++) {

        sysbus_init_mmio(dev, &s->cpuiomem[i]);

        sysbus_init_mmio(sbd, &s->cpuiomem[i]);

    }

    return 0;

}



static void arm_gic_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

    ARMGICClass *agc = ARM_GIC_CLASS(klass);

    agc->parent_init = sbc->init;

    sbc->init = arm_gic_init;



    dc->no_user = 1;

    agc->parent_realize = dc->realize;

    dc->realize = arm_gic_realize;

}



static const TypeInfo arm_gic_info = {