Commit 0a22f8cf authored by Edgar E. Iglesias's avatar Edgar E. Iglesias
Browse files

target-microblaze: Make special registers 64-bit 



Extend special registers to 64-bits. This is in preparation for
MFSE/MTSE, moves to and from extended special registers.

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent ab6dd380

linux-user/microblaze/cpu_loop.c

+2 −2
Original line number Diff line number Diff line
@@ -105,7 +105,7 @@ void cpu_loop(CPUMBState *env) 
                    queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);

                    break;

                default:

                    printf ("Unhandled hw-exception: 0x%x\n",

                    printf("Unhandled hw-exception: 0x%" PRIx64 "\n",

                           env->sregs[SR_ESR] & ESR_EC_MASK);

                    cpu_dump_state(cs, stderr, fprintf, 0);

                    exit(EXIT_FAILURE);

target/microblaze/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -243,7 +243,7 @@ struct CPUMBState { 


    uint32_t imm;

    uint32_t regs[32];

    uint32_t sregs[14];

    uint64_t sregs[14];

    float_status fp_status;

    /* Stack protectors. Yes, it's a hw feature.  */

    uint32_t slr, shr;

target/microblaze/helper.c

+10 −5
Original line number Diff line number Diff line
@@ -143,7 +143,8 @@ void mb_cpu_do_interrupt(CPUState *cs) 
            env->sregs[SR_MSR] |= MSR_EIP;



            qemu_log_mask(CPU_LOG_INT,

                          "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",

                          "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "

                          "esr=%" PRIx64 " iflags=%x\n",

                          env->sregs[SR_PC], env->sregs[SR_EAR],

                          env->sregs[SR_ESR], env->iflags);

            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
@@ -166,7 +167,8 @@ void mb_cpu_do_interrupt(CPUState *cs) 
                /* was the branch immprefixed?.  */

                if (env->bimm) {

                    qemu_log_mask(CPU_LOG_INT,

                                  "bimm exception at pc=%x iflags=%x\n",

                                  "bimm exception at pc=%" PRIx64 " "

                                  "iflags=%x\n",

                                  env->sregs[SR_PC], env->iflags);

                    env->regs[17] -= 4;

                    log_cpu_state_mask(CPU_LOG_INT, cs, 0);
@@ -184,7 +186,8 @@ void mb_cpu_do_interrupt(CPUState *cs) 
            env->sregs[SR_MSR] |= MSR_EIP;



            qemu_log_mask(CPU_LOG_INT,

                          "exception at pc=%x ear=%x iflags=%x\n",

                          "exception at pc=%" PRIx64 " ear=%" PRIx64 " "

                          "iflags=%x\n",

                          env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);

            log_cpu_state_mask(CPU_LOG_INT, cs, 0);

            env->iflags &= ~(IMM_FLAG | D_FLAG);
@@ -221,7 +224,8 @@ void mb_cpu_do_interrupt(CPUState *cs) 
            }

#endif

            qemu_log_mask(CPU_LOG_INT,

                         "interrupt at pc=%x msr=%x %x iflags=%x\n",

                         "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x "

                         "iflags=%x\n",

                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);



            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
@@ -239,7 +243,8 @@ void mb_cpu_do_interrupt(CPUState *cs) 
            assert(!(env->iflags & D_FLAG));

            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;

            qemu_log_mask(CPU_LOG_INT,

                        "break at pc=%x msr=%x %x iflags=%x\n",

                        "break at pc=%" PRIx64 " msr=%" PRIx64 " %x "

                        "iflags=%x\n",

                        env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);

            log_cpu_state_mask(CPU_LOG_INT, cs, 0);

            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);

target/microblaze/mmu.c

+2 −1
Original line number Diff line number Diff line
@@ -240,7 +240,8 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) 
            i = env->mmu.regs[MMU_R_TLBX] & 0xff;

            if (rn == MMU_R_TLBHI) {

                if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))

                    qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%x\n",

                    qemu_log_mask(LOG_GUEST_ERROR,

                             "invalidating index %x at pc=%" PRIx64 "\n",

                             i, env->sregs[SR_PC]);

                env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;

                mmu_flush_idx(env, i);

target/microblaze/op_helper.c

+5 −4
Original line number Diff line number Diff line
@@ -94,16 +94,17 @@ void helper_debug(CPUMBState *env) 
{

    int i;



    qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);

    qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",

    qemu_log("PC=%" PRIx64 "\n", env->sregs[SR_PC]);

    qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "

             "debug[%x] imm=%x iflags=%x\n",

             env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],

             env->debug, env->imm, env->iflags);

    qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",

             env->btaken, env->btarget,

             (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",

             (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",

             (env->sregs[SR_MSR] & MSR_EIP),

             (env->sregs[SR_MSR] & MSR_IE));

             (bool)(env->sregs[SR_MSR] & MSR_EIP),

             (bool)(env->sregs[SR_MSR] & MSR_IE));

    for (i = 0; i < 32; i++) {

        qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);

        if ((i + 1) % 4 == 0)