Commit 06e5cf7a authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Report S/NS status in the CPU debug logs 



If this CPU supports EL3, enhance the printing of the current
CPU mode in debug logging to distinguish S from NS modes as
appropriate.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 1445883178-576-3-git-send-email-peter.maydell@linaro.org
parent 08b8e0f5

target-arm/translate-a64.c

+10 −1
Original line number Diff line number Diff line
@@ -127,6 +127,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, 
    uint32_t psr = pstate_read(env);

    int i;

    int el = arm_current_el(env);

    const char *ns_status;



    cpu_fprintf(f, "PC=%016"PRIx64"  SP=%016"PRIx64"\n",

            env->pc, env->xregs[31]);
@@ -138,12 +139,20 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, 
            cpu_fprintf(f, " ");

        }

    }

    cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n",



    if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {

        ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";

    } else {

        ns_status = "";

    }



    cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",

                psr,

                psr & PSTATE_N ? 'N' : '-',

                psr & PSTATE_Z ? 'Z' : '-',

                psr & PSTATE_C ? 'C' : '-',

                psr & PSTATE_V ? 'V' : '-',

                ns_status,

                el,

                psr & PSTATE_SP ? 'h' : 't');

target-arm/translate.c

+11 −1
Original line number Diff line number Diff line
@@ -11602,6 +11602,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 
    CPUARMState *env = &cpu->env;

    int i;

    uint32_t psr;

    const char *ns_status;



    if (is_a64(env)) {

        aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags);
@@ -11616,13 +11617,22 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 
            cpu_fprintf(f, " ");

    }

    psr = cpsr_read(env);

    cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",



    if (arm_feature(env, ARM_FEATURE_EL3) &&

        (psr & CPSR_M) != ARM_CPU_MODE_MON) {

        ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";

    } else {

        ns_status = "";

    }



    cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",

                psr,

                psr & (1 << 31) ? 'N' : '-',

                psr & (1 << 30) ? 'Z' : '-',

                psr & (1 << 29) ? 'C' : '-',

                psr & (1 << 28) ? 'V' : '-',

                psr & CPSR_T ? 'T' : 'A',

                ns_status,

                cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);



    if (flags & CPU_DUMP_FPU) {