Commit 037c13c5 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement the ARMv8.1-HPD extension 



Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply
interpret the bits as if ARMv8.1-HPD is present without checking.
We will need a slightly different check for hpd for aarch32.

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-10-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent ea22747c

target/arm/cpu64.c

+4 −0
Original line number Diff line number Diff line
@@ -324,6 +324,10 @@ static void aarch64_max_initfn(Object *obj) 
        t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);

        cpu->isar.id_aa64pfr0 = t;



        t = cpu->isar.id_aa64mmfr1;

        t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */

        cpu->isar.id_aa64mmfr1 = t;



        /* Replicate the same data to the 32-bit id registers.  */

        u = cpu->isar.id_isar5;

        u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */

target/arm/helper.c

+20 −7
Original line number Diff line number Diff line
@@ -9636,6 +9636,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 
    bool ttbr1_valid = true;

    uint64_t descaddrmask;

    bool aarch64 = arm_el_is_aa64(env, el);

    bool hpd = false;



    /* TODO:

     * This code does not handle the different format TCR for VTCR_EL2.
@@ -9750,6 +9751,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 
        if (tg == 2) { /* 16KB pages */

            stride = 11;

        }

        if (aarch64) {

            if (el > 1) {

                hpd = extract64(tcr->raw_tcr, 24, 1);

            } else {

                hpd = extract64(tcr->raw_tcr, 41, 1);

            }

        }

    } else {

        /* We should only be here if TTBR1 is valid */

        assert(ttbr1_valid);
@@ -9765,6 +9773,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 
        if (tg == 1) { /* 16KB pages */

            stride = 11;

        }

        if (aarch64) {

            hpd = extract64(tcr->raw_tcr, 42, 1);

        }

    }



    /* Here we should have set up all the parameters for the translation:
@@ -9883,15 +9894,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 
            break;

        }

        /* Merge in attributes from table descriptors */

        attrs |= nstable << 3; /* NS */

        if (hpd) {

            /* HPD disables all the table attributes except NSTable.  */

            break;

        }

        attrs |= extract32(tableattrs, 0, 2) << 11;     /* XN, PXN */

        attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */

        /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1

         * means "force PL1 access only", which means forcing AP[1] to 0.

         */

        if (extract32(tableattrs, 2, 1)) {

            attrs &= ~(1 << 4);

        }

        attrs |= nstable << 3; /* NS */

        attrs &= ~(extract32(tableattrs, 2, 1) << 4);   /* !APT[0] => AP[1] */

        attrs |= extract32(tableattrs, 3, 1) << 5;      /* APT[1] => AP[2] */

        break;

    }

    /* Here descaddr is the final physical address, and attributes