Commit ea22747c authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Tidy scr_write 



Because EL3 has a fixed execution mode, we can properly decide
which of the bits are RES{0,1}.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-8-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 619959c3

target/arm/cpu.h

+0 −2
Original line number Diff line number Diff line
@@ -1312,8 +1312,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 
#define SCR_FIEN              (1U << 21)

#define SCR_ENSCXT            (1U << 25)

#define SCR_ATA               (1U << 26)

#define SCR_AARCH32_MASK      (0x3fff & ~(SCR_RW | SCR_ST))

#define SCR_AARCH64_MASK      (0x3fff & ~SCR_NET)



/* Return the current FPSCR value.  */

uint32_t vfp_get_fpscr(CPUARMState *env);

target/arm/helper.c

+9 −5
Original line number Diff line number Diff line
@@ -1279,11 +1279,15 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, 


static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

{

    /* We only mask off bits that are RES0 both for AArch64 and AArch32.

     * For bits that vary between AArch32/64, code needs to check the

     * current execution mode before directly using the feature bit.

     */

    uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;

    /* Begin with base v8.0 state.  */

    uint32_t valid_mask = 0x3fff;



    if (arm_el_is_aa64(env, 3)) {

        value |= SCR_FW | SCR_AW;   /* these two bits are RES1.  */

        valid_mask &= ~SCR_NET;

    } else {

        valid_mask &= ~(SCR_RW | SCR_ST);

    }



    if (!arm_feature(env, ARM_FEATURE_EL2)) {

        valid_mask &= ~SCR_HCE;