MIPS/opcodes: Rework INSN_* flags into a consistent block

For historic reasons we have ended up with a random set of discontiguous
bit assignments for INSN_* flags within `membership' and `exclusions'
members of `mips_opcode'.  Some of the bits were previously used for ASE
assignments and have been reused in a disorganised fashion since `ase'
has been split off as a member on its own.  It makes them hard to track
and maintain, and to see how many we still have available for future
assignments.

Therefore reorder the flags using consecutive bits and matching the
order used with the switch statement in `cpu_is_member'.