MIPS: sync oprand char usage between mips and micromips

We should try our best to make mips32 using the same
oprand char with micromips. So for mips32, we use:

  ^  is added for 5bit sa oprand for some new DSPr2 instructions:
	APPEND, PREPEND, PRECR_SRA[_R].PH.W
	the LSB bit is 11, like RD.
  +t is removed for coprocessor 0 destination register.
	'E' does the samething.
  +t is now used for RX oprand for MFTR/MTTR (MT ASE)
  ?  is added for sel oprand for MFTR/MTTR (MT ASE)
	For mips32, the position of sel in MFTR/MTTR is same with mfc0 etc,
	while for micromips, they are different.

We also add an extesion format of cftc2/cttc2/mftc2/mfthc2/mttc2/mtthc2:
	concatenating rs with rx as the index of control or data.