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Commit 3224e32f authored by Jaydeep Patil's avatar Jaydeep Patil Committed by Andrew Burgess
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sim: riscv: Add support for compressed integer instructions



Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.

Approved-By: default avatarAndrew Burgess <aburgess@redhat.com>
parent 4dad3c1e
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