Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}

Omitting predicate size specifier in vector form of {sq, uq, }{decp, incp} is deprecated and will be prohibited in a future release of the aarch64,
see https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions/DECP--vector---Decrement-vector-by-count-of-true-predicate-elements-

.

This allows explicit size specifier, e.g. `decp z0.h, p0.h`, for predicate operand of these SVE instructions.
The existing behaviour of not requiring the specifier is preserved.
And the disasembly is with the specifier with this patch.

The GAS tests passed under our local tests.

opcodes/
	* aarch64-asm.c: Modify `sve_size_hsd` encoding.
	* aarch64-tbl.h (aarch64_opcode_table): Add QUALS's type OP_SVE_Vv_HSD
	for decp, incp, sqdecp, sqincp, uqdecp and uqincp.

gas/
	* testsuite/gas/aarch64/sve-movprfx_23.s: Update movprfx_23 testcase's
	test_sametwo macro, where take the predicate size specifier.
	* testsuite/gas/aarch64/sve-movprfx_23.d: Update movprfx_23 testcase's
	expected disassembly.
	* testsuite/gas/aarch64/sve-movprfx_23.l: Update movprfx_23 testcase's
	expected assembler messages.
	* testsuite/gas/aarch64/sve.s: Add sve testcase's instructions for
	decp, incp, sqdecp, sqincp, uqdecp and uqincp, which take the
	predicate size specifier.
	* testsuite/gas/aarch64/sve.d: Update sve testcase's expected
	disassembly.

Signed-off-by: CaiJingtao <caijingtao@huawei.com>