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Commit ff46c610 authored by Gerhard Engleder's avatar Gerhard Engleder Committed by David S. Miller
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dt-bindings: net: tsnep: Allow dma-coherent



Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
of AXI master ports. Also cache coherent AXI master ports are available.
The property "dma-coherent" is used to signal that DMA is cache
coherent.

Add "dma-coherent" property to allow the configuration of cache coherent
DMA.

Signed-off-by: default avatarGerhard Engleder <gerhard@engleder-embedded.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d742ea6b
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