scsi: ufs: add missing memory barriers

Performing several writes to UFS host controller registers has no
guarantee of ordering, so we must make sure register writes to setup
request list base address etc. are performed before the run/stop
register is enabled.  In addition, when setting up a task request, we
must make sure the updating of descriptors takes places before ringing
the doorbell, similarly to setting up a transfer request.

Reviewed-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>