clk: socfpga: stratix10: fix divider entry for the emac clocks (74684cce) · Commits · Mirrors / github.com / sifive_riscv-linux

Commit 74684cce authored Jun 07, 2019 by

Dinh Nguyen Committed by Stephen Boyd Jun 25, 2019

clk: socfpga: stratix10: fix divider entry for the emac clocks



The fixed dividers for the emac clocks should be 2 not 4.

Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent c8edb316

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