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Commit 4ccc402e authored by Thierry Reding's avatar Thierry Reding Committed by Peter De Schrijver
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clk: tegra: Fix enabling of PLLE 



When enabling the PLLE as its final step, clk_plle_enable() would
accidentally OR in the value previously written to the PLLE_SS_CTRL
register.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent c61e4e75
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