clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2
Add clock and reset support for the SDHI1 and SDHI2 blocks on the RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231010132701.1658737-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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