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Commit 438c61a7 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'v6.6-rockchip-clk1' of...

Merge tag 'v6.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - PLL rates for rk3568 and the display clock tree for rv1126 which wasn't present before

* tag 'v6.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rv1126: Add PD_VO clock tree
  clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
  clk: rockchip: rk3568: Add PLL rate for 101MHz
parents 06c2afb8 5c7a71fd
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