- Aug 06, 2017
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Yakir Yang authored
Add an edp node, and also add edp endpoints to vopb and vopl output port nodes. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Elaine Zhang authored
1. add pd node for RK3399 Soc 2. create power domain tree 3. add qos node for domain Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Mark Yao authored
Add devicetree nodes for rk3399 VOP (Video Output Processors), and the top level display-subsystem root node. Later patches add endpoints (eDP, HDMI, MIPI, etc) that attach to the VOPs' output ports. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Jianqun Xu authored
Add opp tables for cpu cluster0 and cluster1 by including rk3399-opp.dtsi. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Finley Xiao authored
This patch adds basic OPP entries for RK3328 SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 01, 2017
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Caesar Wang authored
This patch updates the dynamic-power-coefficient for big cluster on rk3399 SoCs. The dynamic power consumption of the CPU is proportional to the square of the Voltage (V) and the clock frequency (f). The coefficient is used to calculate the dynamic power as below - Pdyn = dynamic-power-coefficient * V^2 * f Where Voltage is in uV, frequency is in MHz. As the following is the tested data on rk3399's big cluster. frequency(MHz) Voltage(V) Current(mA) Dynamic-power-coefficient 24 0.8 15 48 0.8 23 ~417 96 0.8 40 ~443 216 0.8 82 ~438 312 0.8 115 ~430 408 0.8 150 ~455 So the dynamic-power-coefficient average value is about 436. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jul 30, 2017
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Sugar Zhang authored
This patch add the spdif dt node for rk3328. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Sugar Zhang authored
This patch add the spdif dt node for rk3368 soc. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jul 26, 2017
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Shawn Lin authored
This allows basic support for SD highspeed cards but no UHS-I mode got ready due to the propagated defer-probe error from RK805. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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David Wu authored
Add the core grf subnode for the io-domain controller. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jul 23, 2017
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Shawn Lin authored
Kill these two pinctrl reference totally from rk3399 as it never work indeed. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
pcie_clkreqn actually doesn't work at all, so replace it with pcie_clkreqn_cpm. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Caesar Wang authored
This patch enables the gpu and adds the mali-supply power for RK3399-GRU devices. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Caesar Wang authored
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq opp table. RK3399 and RK3399-OP1 SoCs have a different recommendation table with gpu opp. Also, the ARM's mali driver found on https://developer.arm.com/products/software/mali-drivers/midgard-kernel . Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
keep-power-in-suspend was invented for SDIO only, so it should not be used for eMMC node. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jul 16, 2017
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Shawn Lin authored
We deprecated the "num-slots" property now and plan to get rid of it finally. Just move a step to cleanup it from DT. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
pcie_clkreqn actually doesn't work at all, so replace it with pcie_clkreqn_cpm. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Caesar Wang authored
The SdioAudio power domain includes the i2s/spdif/spi5/sdio. So this patch adds the pd control for rk3399 i2s/spdif/spi5/sdio, in order to save more power consumption. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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William Wu authored
Rockchip's RK3328 evaluation board has one usb2 otg controller and one usb2 host controller which consist of EHCI and OHCI. Each usb controller connects with one usb2 phy port through UTMI+ interface. Let's enable them to support usb2 on RK3328 evaluation board. Signed-off-by: William Wu <william.wu@rock-chips.com> [restructured enablement of u2phy subnodes] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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William Wu authored
This patch adds usb2 otg/host controllers and phys nodes for Rockchip RK3328 SoCs. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Brian Norris authored
Provide the dynamic power coefficient of the big and little CPU clusters. These numbers are currently in use on the Samsung Chromebook Plus ("Kevin"). The power allocator thermal governor doesn't know how to do anything if it doesn't get power parameters from its cooling devices (in this case, CPUfreq). So this effectively enables the power-allocator governor. Signed-off-by: Brian Norris <briannorris@chromium.org> [set the property in each core node] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Matthias Kaehlcke authored
The Gru device tree currently contains entries for the regulators ppvar_bigcpu, ppvar_litcpu, ppvar_gpu and ppvar_centerlogic; however, the regulators have not been enabled, due to the lack of binding and driver support for keeping the over-voltage protection (OVP) at bay and preventing unintended regulator shutdowns on voltage downshifts. Now, the vctrl regulator driver has been merged, along with new bindings for asymmetric settling time. The driver is OVP aware, it splits larger voltage decreases in multiple steps when necessary and adds required delays. This change renames each of the aforementioned regulators to <orig_name>_pwm and adds a new vctrl regulator named <orig_name>. The vctrl regulators use the voltage of their corresponding PWM regulator as control voltage. The OVP related values are empirical and stem from the Chrome OS kernel tree. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Brian Norris <briannorris@chromium.org> [fixed node names and parent supplies of gpu and centerlogic] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Matthias Kaehlcke authored
Gru derivatives besides Kevin have slightly different voltage ranges for their CPU regulators. Let's keep the base Gru file accurate and let Kevin override. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Klaus Goger authored
replace all occurrences of sdmcc with sdmmc in the arm64 rockchip devicetree files. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- May 30, 2017
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Heiko Stuebner authored
The rk3399 has multiple variants with different frequency ratings. The operating points currently in the kernel stem from the op1 variant used in Gru ChromeOS devices and may not be suitable for general rk3399 chips. Therefore bring it back to the official general operating points. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner authored
The OP1 is a rk3399 variant used in ChromeOS devices with a slightly higher frequency rating compared to the regular rk3399, but right now the only available operating points don't match either variant with both needing adjustments to actually fit their specs. Therefore introduce separate operting points, from the ChromeOS kernel, for the OP1 and use it on Gru devices. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner authored
This allows basic usage of usb3 devices but no typec specific things yet. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner authored
This is used by bootloaders to override the mac address in the devicetree if needed. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner authored
The power-tree on the rk3399-firefly did not completely match the documentation and vendor devicetree. It was also missing some supply-hirarchy information and some regulator-gpio names did not match the schematics. Fix this for the existing regulators before introducing new things. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
This patch adds sdmmc, sdio, emmc nodes for Rockchip RK3328 SoCs. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- May 23, 2017
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Shawn Lin authored
Make full use of 32 regions and increase IORESOURCE_MEM_64 so that we could have more chance to support PCIe switch with more endpoints attached to our RC. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
In order to support multiple hierarchy of PCIe buses, for instance, PCIe switch, we need to extent bus-ranges to as max as possible. We have 32 regions and could support up to 31 buses except bus 0 for our root bridge. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Kever Yang authored
Add pinctrl for sdio, sdmmc, pcie, spdif, hdmi. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Kever Yang authored
Add qos setting reg for some peripheral like sd, usb, pcie. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- May 19, 2017
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Arnd Bergmann authored
The way we handle include paths for DT has changed a bit, which broke a file that had an unconventional way to reference a common header file: arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts:47:10: fatal error: include/dt-bindings/input/linux-event-codes.h: No such file or directory This removes the leading "include/" from the path name, which fixes it. Fixes: d5d332d3 ("devicetree: Move include prefixes from arch to separate directory") Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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- May 14, 2017
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Kever Yang authored
Firefly-rk3399 is a bord from T-Firefly, you can find detail about it here: http://en.t-firefly.com/en/firenow/Firefly_RK3399/ This patch add basic node for the board and make it able to bring up. Peripheral works: - usb hub which connect to ehci controller; - UART2 debug - eMMC - PCIe Not work: - USB 3.0 HOST, type-C port - sdio, sd-card Not test for other peripheral: - HDMI - Ethernet - OPTICAL - WiFi/BT - MIPI CSI/DSI - IR - EDP/DP Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Apr 08, 2017
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Andy Yan authored
Commit 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board") sets the memory size to 2 GB, but this board only has 1 GB DRAM, so change it to the correct value here. Fixes: 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board") Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Apr 05, 2017
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Liang Chen authored
This patch add rk3328-evb.dts for RK3328 evaluation board. Tested on RK3328 evb. Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Liang Chen authored
This patch adds core dtsi file for Rockchip RK3328 SoCs. Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Mar 23, 2017
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Brian Norris authored
We need to enable this regulator before the digitizer can be used. Wacom recommended waiting for 100 ms before talking to the HID. Signed-off-by: Brian Norris <briannorris@chromium.org> [store chip ident as comment until i2c multi-compatibles are sorted] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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