- Feb 25, 2016
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Lars Persson authored
Signed-off-by:
Lars Persson <larper@axis.com> Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Lars Persson authored
Initial device tree for the Artpec-6 SoC. Signed-off-by:
Lars Persson <larper@axis.com> Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Sudeep Holla authored
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source. Few dts files assign value "1" to gpio-key,wakeup which is incorrect. Since the presence of the boolean property indicates it is enabled, value of "0" or "1" have no significance. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property which inturn fixes the above mentioned issue. Reviewed-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- Feb 11, 2016
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Maxime Coquelin authored
STM32F429 allows to remap FMC SDRAM Bank 1 from 0xc0000000 to 0x0, by writing 0x4 to SYSCFG_MEMRMP register. As mentionned in the reference manual (see chapter 9.3.1), the performance gain is really interresting: "In remap mode at address 0x0000 0000, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance." These are the dhrystone results with and without the remap enabled: Default (SDRAM in 0xc0000000): --------------------------------- Microseconds for one run through Dhrystone: 31.8 Dhrystones per Second: 31416.9 Remap (SDRAM in 0x0000000): ----------------------------- Microseconds for one run through Dhrystone: 20.6 Dhrystones per Second: 48520.1 This patch first change the SDRAM start address to 0x0 for STM32429i-EVAL board, and also set the dma-range property as the other masters than the M4 CPU still see SDRAM in 0xc0000000. Note that the Discovery board cannot benefit from this feature, since the SDRAM is connected to Bank 2. Signed-off-by:
Maxime Coquelin <mcoquelin.stm32@gmail.com>
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Maxime Coquelin authored
Acked-by:
Patrice Chotard <patrice.chotard@st.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Maxime Coquelin <mcoquelin.stm32@gmail.com>
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Maxime Coquelin authored
This patch selects USART1 pin configuration on PA9/PA10 pins for both Eval and Disco boards. Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
Maxime Coquelin <mcoquelin.stm32@gmail.com>
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Maxime Coquelin authored
The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank. Acked-by:
Patrice Chotard <patrice.chotard@st.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Maxime Coquelin <mcoquelin.stm32@gmail.com>
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Vladimir Zapolskiy authored
The change adds fixed voltage regulator for SD controller, ARM MMCI controller driver uses it to control card power management. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com>
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Vladimir Zapolskiy authored
Phytec PHY3250 board has GPIO controlled regulators for LCD and backlight, add their descriptions to board DTS file. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com>
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Vladimir Zapolskiy authored
LPC32xx interrupt controller has two cells, instead of zero specify proper irq types for all consumers. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com>
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Vladimir Zapolskiy authored
If clock-frequency property is given, then it substitutes calculation of supplying clock frequency from parent clock, this may break UART, if parent clock is given and managed by common clock framework. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com>
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Vladimir Zapolskiy authored
The change adds device node of LPC32xx USB clock controller and adds clock properties to USB OHCI, USB device and I2C controller to USB phy device nodes. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com>
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Vladimir Zapolskiy authored
The change adds clock properties to all described peripheral devices, clock ids are taken from dt-bindings/clock/lpc32xx-clock.h Some existing drivers expect to get clock names, in those cases clock-names are added as well. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com>
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Vladimir Zapolskiy authored
NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part of system control block (SCB). CPC is supplied by two external oscillators and it manages core and most of peripheral clocks, the change adds SCB and CPC descriptions to shared LPC32xx dtsi file. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com>
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Vladimir Zapolskiy authored
NXP LPC32xx SoC has two external oscillators - one is mandatory and always on 32768 Hz oscillator and one optional 10-20MHz oscillator, which is practically always present on LPC32xx boards, because its presence is needed to supply USB controller clock and by default it supplies ARM and most of the peripheral clocks, LPC32xx User's Manual references it as a main oscillator. The change adds device nodes for both oscillators, frequency of the main oscillator is selected to be 13MHz by default, this variant is found on all LPC32xx reference boards. The device nodes for external oscillators are needed to describe input clocks of LPC32xx clock controller. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com>
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James Chao authored
The LOCK key is at KSO9/KSI3 for Chromebook Flip and other devices that use the Chrome OS EC keyboard matrix. Signed-off-by:
James Chao <james_chao@asus.com> Signed-off-by:
YH Huang <yh.huang@mediatek.com> Signed-off-by:
Daniel Kurtz <djkurtz@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Feb 10, 2016
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Liviu Dudau authored
ARM's Juno platforms have two HDLCD controllers, each linked to an NXP TDA19988 HDMI transmitter that provides output encoding. Add them to the device tree. Acked-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
Liviu Dudau <Liviu.Dudau@arm.com>
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Sudeep Holla authored
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source. Few dts files assign value "1" to gpio-key,wakeup and in one instance a value "0" is assigned probably assuming it won't be enabled as a wakeup source. Since the presence of the boolean property indicates it is enabled, value of "0" have no value. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property which inturn fixes the above mentioned issue. Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Feb 09, 2016
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Sudeep Holla authored
Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by Cortex A72 cores. Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
The PCIe controller is found on all Juno SoC version. However it's not functional on R0 due to some hardware bug. In preparation to add Juno R2 support, this patch moves the pcie-controller defination to base DTS file. It's marked as disabled by default and is enabled for Juno R1 explicitly. Acked-by:
Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Andre Przywara authored
The ARMv8 Foundation model sports a command line parameter to use a GICv3 emulation instead of the default GICv2 interrupt controller. Add a new .dts file which reuses most of the definitions of the existing model while just adding the required properties for the GICv3 node. This allows the public Foundation model to run with a GICv3. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Andre Przywara authored
The ARMv8 Foundation model can be run with a GICv2 or a GICv3. To prepare for the GICv3 version of the .dts without code duplication, move most of the nodes of the existing DT (except the GIC) into an include file and just keep that include statement and the GIC node in the current foundation-v8.dts. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Acked-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Andre Przywara authored
The Foundation model GIC mapping is wrong, as the GICC region should be 8kB instead of 4kB (the model implements the GICv2 architecture). This defect prevents the driver from switching to EOImode==1. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Reviewed-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Andre Przywara authored
To prepare the ARM foundation model to support GICv3, we adjust the #address-cells property of the current GICv2 node to be compatible with the two cells required for GICv3 later. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Acked-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Mario Lange authored
Add dts file to support Buffalo Linkstation LS-QVL, which is marvell kirkwood based 4-bay 3.5" HDD NAS. Product info: - (JPN) http://buffalo.jp/product/hdd/network/ls-qvl_r5/ - (ENG) http://www.buffalotech.com/products/network-storage/home-and-small-office/linkstation-pro-quad Signed-off-by:
Mario Lange <mario_lange@gmx.net> Signed-off-by:
Roger Shimizu <rogershimizu@gmail.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Aaro Koskinen authored
Fix audio on kirkwood-openrd-client: 1) The audio-controller was left disabled. 2) The probe fails because cs42l51 is missing #sound-dai-cells. /sound/simple-audio-card,codec: could not get #sound-dai-cells for /ocp@f1000000/i2c@11000/cs42l51@4a asoc-simple-card sound: parse error -22 asoc-simple-card: probe of sound failed with error -22 3) The mapping is incorrect: asoc-simple-card sound: cs42l51-hifi <-> spdif mapping ok should be: asoc-simple-card sound: cs42l51-hifi <-> i2s mapping ok Reported-by:
Rick Thomas <rbthomas@pobox.com> Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Tested-by:
Rick Thomas <rbthomas@pobox.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Aaro Koskinen authored
Some OpenRD boards have RS-232 and RS-486 connectors wired, but using them needs a custom DTB as the current DTB configures SD card slot instead. This patch adds documentation into the DTS on how to change the configuration. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Roger Shimizu authored
LS-WVL/VL are both kirkwood-6282 based NAS devices, which share many MPP pins. However they are slightly different: - LS-WVL is 2-Bay NAS, and LS-VL is only 1-Bay. - There're two red LED indicator on LS-WVL to show when HDD fails, which is similar to LS-WXL, but there's no such on LS-VL. So after the split, common part goes into .dtsi file: - kirkwood-linkstation-6282.dtsi while all rest part goes into device specific .dts file: - kirkwood-linkstation-lsvl.dts - kirkwood-linkstation-lswvl.dts Signed-off-by:
Roger Shimizu <rogershimizu@gmail.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Roger Shimizu authored
LS-WXL/WSXL are both kirkwood-6281 based 2-Bay NAS devices, which share many MPP pins. However they are slightly different: - There're two red LED indicator on LS-WXL to show when HDD fails, but there's no such on LS-WSXL. - There's 4-level speed adjustable FAN on LS-WXL, but not LS-WSXL. So after the split, common part goes into .dtsi file: - kirkwood-linkstation.dtsi - kirkwood-linkstation-duo-6281.dtsi while all rest part goes into device specific .dts file: - kirkwood-linkstation-lswsxl.dts - kirkwood-linkstation-lswxl.dts Signed-off-by:
Roger Shimizu <rogershimizu@gmail.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Roger Shimizu authored
Signed-off-by:
Roger Shimizu <rogershimizu@gmail.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Aaro Koskinen authored
The SD card slot was enabled by default with legacy booting. It does not work anymore with DT boot. Fix by providing GPIO configuration that matches the old default. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Aaro Koskinen authored
The UART/SD pin names are swapped, fix that. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Gregory CLEMENT authored
Since the commit a526973e ("pinctrl: mvebu: Fix mapping of pin 63 (gpo -> gpio)"), the mpp63 is no more declared as a GPO but is a GPIO. Even if in the datasheet this pin is described as GPO, the experience of the D-Link DNS-327L board shows that it can be used as a GPIO. This commits generated warnings for the board using this pin as gpo, with this patch the dts are fixed by using the new function (gpio) instead of the old one. The binding documentation has also been updated accordingly. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by:
Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
Using the usb-nop-xceiv PHY for the xhci nodes allows a better representation of the hardware but also a better handling of the regulator. By linking the regulator to the PHY there is no more need to use the regulator-always-on property, then it allows a better power management. The remaining usb node uses the ehci-orion driver which can't be used with the usb-nop-xceiv PHY and must keeps the direct link to the regulator with the regulator-always-on property. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
Really, what we meant by regulator-always-on is that the regulators are already turned on by the bootloader, for which regulator-boot-on is a better description. A net advantage of using regulator-boot-on is that the regulator is not touched at boot time by the kernel, which avoids having the hard drives spinning down and then up again, taking several (~5) seconds of additional boot time. In addition, there is no need to have such properties on the child regulators used for SATA. Having it on the parent regulator that really controls the GPIO is sufficient. Without the patch: [ 3.945866] ata2: SATA link down (SStatus 0 SControl 300) [ 3.995862] ata3: SATA link down (SStatus 0 SControl 300) [ 4.005863] ata4: SATA link down (SStatus 0 SControl 300) [ 9.125861] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) [ 9.144575] ata1.00: ATA-8: WDC WD5003ABYX-01WERA1, 01.01S02, max UDMA/133 [ 9.151471] ata1.00: 976773168 sectors, multi 0: LBA48 NCQ (depth 31/32) (and you can hear the disk spinning down and up during this 5.1 seconds delay) With the patch: [ 3.945988] ata2: SATA link down (SStatus 0 SControl 300) [ 4.005980] ata4: SATA link down (SStatus 0 SControl 300) [ 4.011404] ata3: SATA link down (SStatus 0 SControl 300) [ 4.145978] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) [ 4.153701] ata1.00: ATA-8: WDC WD5003ABYX-01WERA1, 01.01S02, max UDMA/133 [ 4.160597] ata1.00: 976773168 sectors, multi 0: LBA48 NCQ (depth 31/32) Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
As the name of the Device Tree file name suggests, the Armada 388 GP really contains an Armada 388 SoC, so this commit updates the board name and compatible string in the Device Tree file. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Caesar Wang authored
Pl330 integrated in rk3036 platform that doesn't support DMAFLUSHP function. So we add 'arm,pl330-broken-no-flushp' quirk for rk3036. Signed-off-by:
Caesar Wang <wxt@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
Pl330 integrated in rk3xxx platform doesn't support DMAFLUSHP function. So we add arm,pl330-broken-no-flushp quirk for it. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
Caesar Wang <wxt@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Addy Ke authored
Pl330 integrated in rk3288 platform doesn't support DMAFLUSHP function. So we add arm,pl330-broken-no-flushp quirk for it. Signed-off-by:
Addy Ke <addy.ke@rock-chips.com> Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by:
Doug Anderson <dianders@chromium.org> Reviewed-by:
Sonny Rao <sonnyrao@chromium.org> Signed-off-by:
Caesar Wang <wxt@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Feb 06, 2016
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Nicolai Stange authored
Commit 16da3068 ("um: kill pfn_t") introduced a compile warning for defconfig (SUBARCH=i386): arch/um/kernel/skas/mmu.c:38:206: warning: right shift count >= width of type [-Wshift-count-overflow] Aforementioned patch changes the definition of the phys_to_pfn() macro from ((pfn_t) ((p) >> PAGE_SHIFT)) to ((p) >> PAGE_SHIFT) This effectively changes the phys_to_pfn() expansion's type from unsigned long long to unsigned long. Through the callchain init_stub_pte() => mk_pte(), the expansion of phys_to_pfn() is (indirectly) fed into the 'phys' argument of the pte_set_val(pte, phys, prot) macro, eventually leading to (pte).pte_high = (phys) >> 32; This results in the warning from above. Since UML only deals with 32 bit addresses, the upper 32 bits from 'phys' used to be always zero anyway. Also, all page protection flags defined by UML don't use any bits beyond bit 9. Since the contents of a PTE are defined within architecture scope only, the ->pte_high member can be safely removed. Remove the ->pte_high member from struct pte_t. Rename ->pte_low to ->pte. Adapt the pte helper macros in arch/um/include/asm/page.h. Noteworthy is the pte_copy() macro where a smp_wmb() gets dropped. This write barrier doesn't seem to be paired with any read barrier though and thus, was useless anyway. Fixes: 16da3068 ("um: kill pfn_t") Signed-off-by:
Nicolai Stange <nicstange@gmail.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Richard Weinberger <richard@nod.at> Cc: Nicolai Stange <nicstange@gmail.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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