- Sep 13, 2015
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Josh Boyer authored
Commit 79ae3e66 (ARM: dts: sun4i: Add Iteaduino Plus A10) added a new make target for the sun4i-a10-itead-iteaduino-plus dts file, but mistakenly used .dts instead of the correct .dtb suffix. This resulted in a build error like: scripts/Makefile.dtbinst:42: target 'sun4i-a10-itead-iteaduino-plus.dts' doesn't match the target pattern when doing a make dtbs_install. Fix it to use the proper file name. Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Timo Sigurdsson authored
sun7i-a20.dtsi contains a cpufreq operating point at 0.9 volts. The minimum CPU voltage for the Allwinner A20 SoC, however, is 1.0 volts. Thus, raise the voltage for the lowest operating point to 1.0 volts in order to stay within the SoC specifications. It is an undervolted setting that isn't stable across all SoCs and boards out there. Cc: <stable@vger.kernel.org> # v4.0+ Fixes: d96b7161 ("ARM: dts: sun7i: Add cpu clock reference and operating points to dtsi") Signed-off-by: Timo Sigurdsson <public_timo.s@silentcreek.de> Acked-by: Iain Paton <ipaton0@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- Sep 11, 2015
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Yinghai Lu authored
When loading x86 64bit kernel above 4GiB with patched grub2, got kernel gunzip error. | early console in decompress_kernel | decompress_kernel: | input: [0x807f2143b4-0x807ff61aee] | output: [0x807cc00000-0x807f3ea29b] 0x027ea29c: output_len | boot via startup_64 | KASLR using RDTSC... | new output: [0x46fe000000-0x470138cfff] 0x0338d000: output_run_size | decompress: [0x46fe000000-0x47007ea29b] <=== [0x807f2143b4-0x807ff61aee] | | Decompressing Linux... gz... | | uncompression error | | -- System halted the new buffer is at 0x46fe000000ULL, decompressor_gzip is using 0xffffffb901ffffff as out_len. gunzip in lib/zlib_inflate/inflate.c cap that len to 0x01ffffff and decompress fails later. We could hit this problem with crashkernel booting that uses kexec loading kernel above 4GiB. We have decompress_* support: 1. inbuf[]/outbuf[] for kernel preboot. 2. inbuf[]/flush() for initramfs 3. fill()/flush() for initrd. This bug only affect kernel preboot path that use outbuf[]. Add __decompress and take real out_buf_len for gunzip instead of guessing wrong buf size. Fixes: 1431574a (lib/decompressors: fix "no limit" output buffer length) Signed-off-by: Yinghai Lu <yinghai@kernel.org> Cc: Alexandre Courbot <acourbot@nvidia.com> Cc: Jon Medhurst <tixy@linaro.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: <stable@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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- Sep 10, 2015
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Cc: Tim Bird <tim.bird@sonymobile.com> Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Cc: Mathieu Olivari <mathieu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Cc: Mike Rapoport <mike.rapoport@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Add a label to the serial nodes that are being used for the console. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- Sep 06, 2015
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Keerthy authored
rtc can either be supplied from internal 32k clock or external crystal generated 32k clock. Internal clock is SOC specific and the external clock is board dependent. Adding the corresponding nodes. Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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- Aug 28, 2015
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Vincent Donnefort authored
Since the LED modes mapping is no longer hardcoded inside the leds-ns2 driver, then it must be provided through the modes-map property in the ns2-leds nodes. Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
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- Aug 25, 2015
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Linus Walleij authored
The base addresses for the Ux500 PRCC controllers are hardcoded, let's move them to the clock node in the device tree and delete the constants. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- Aug 22, 2015
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Tomeu Vizoso authored
Specify how the GPIOs map to the pins in Tegra SoCs, so the dependency is explicit. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Nicolas Chauvet authored
Current base address is wrong by 0x04 bytes for AHB bus device as shown in dmesg: tegra-ahb 6000c004.ahb: incorrect AHB base address in DT data - enabling workaround To correct old DTBs, commit ce7a10b0 ("ARM: 8334/1: amba: tegra-ahb: detect and correct bogus base address") checks for the low bit of the base address and removes theses 0x04 bytes at runtime. This patch fixes the original DTS, so upstream version doesn't need the workaround of the base address. As both addresses are valid, this patch doesn't break compatibility. Tested on tegra20-paz00 (aka ac100). Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Kyle Huey authored
This patch modifies the device tree for Tegra124 based devices to enable the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA Tegra K1 TRM (DP-06905-001_v03p). This patch was tested on a Jetson TK1. Signed-off-by: Kyle Huey <khuey@kylehuey.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Alexandre Courbot authored
Add the device-tree node for the GK20A GPU and leave it disabled. It is the responsibility of the bootloader to enable it if the VPR registers have been programmed such that the GPU can operate. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add the device-tree node for the GK20A GPU and leave it disabled. It is the responsibility of the bootloader to enable it if the VPR registers have been programmed such that the GPU can operate. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Alexandre Courbot authored
Nouveau can make use of the IOMMU to make physical appear linear in the GPU address space. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Mikko Perttunen authored
Specify the CPU voltage regulator for the cpufreq driver. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tuomas Tynkkynen authored
The Tegra124 cpufreq driver relies on certain clocks being present in the /cpus/cpu@0 node. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tuomas Tynkkynen authored
Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tuomas Tynkkynen authored
The DFLL clocksource is a separate IP block from the usual clock-and-reset controller, so it gets its own device tree node. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Moritz Fischer authored
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Aug 21, 2015
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Masahiro Yamada authored
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings document says that the bits[15:8] of the 3rd cell of the interrupts property represents PPI interrupt CPU mask. Because the timer interrupts are wired to all of the 4 cores, bits[15:8] should be set to 0xf. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Brian Norris authored
When getting translated from a downstream device tree that used slightly different DT bindings, these regulators got labeled with the "on-in-suspend" state, when they were actually supposed to be turned off for S3 suspend. This was harmless, but not intentional, AFAICT. Let's turn them off to get the optimal power state. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Brian Norris authored
This DTS file was submitted with non-upstream bindings. I happened across this while reviewing the jaq DTS. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 19, 2015
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Stephen Boyd authored
The sp810 clk driver is calling the clk consumer APIs from clk_prepare ops to change the parent to a 1 MHz fixed rate clock for each of the clocks that the driver provides. Use assigned-clock-parents for this instead of doing it in the driver to avoid using the consumer API in provider code. This also allows us to remove the usage of clk provider APIs that take a struct clk as an argument from the sp810 driver. Cc: Pawel Moll <pawel.moll@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Aug 17, 2015
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Mauro Carvalho Chehab authored
There are some missing dependencies at the DT, as it looks for an I2C bus named "ssc2", but this is not defined. Probably, it misses some dependencies from some other tree. For now, revert this patch, to avoid build breakages. This reverts commit 5d8877b6. Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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- Aug 15, 2015
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Eduardo Valentin authored
This change is a code reorganization. Here we introduce serial_imx_enable_wakeup() helper function to do the job of configuring and preparing wakeup sources on imx serial device. The idea is to allow other parts of the code to call this function whenever the device is known to go to idle. Cc: Fabio Estevam <festevam@gmail.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- Aug 14, 2015
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Mugunthan V N authored
CPSW driver has been updated with compatibles for enabling errata workarounds. So updating cpsw compatibles. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Mugunthan V N authored
CPSW driver has been updated with compatibles for enabling errata workarounds. So updating cpsw compatibles. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Marek Szyprowski authored
JPEG codec node has been added in parallel to the patch, which added support for IOMMU to Exynos platform, so JPEG device for Exynos4 SoCs lacked IOMMU property. This patch fixes this issue. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Alexis Ballier authored
SPI1 is available on IO Port #2 (as depicted on their website) in PCB Revision 0.5 of Hardkernel Odroid U3 board. The shield connects a 256KiB spi-nor flash on that bus. Signed-off-by: Alexis Ballier <aballier@gentoo.org> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Michal Suchanek authored
Although there is only one choice of chipselect it is necessary to specify it. The driver cannot claim the gpio otherwise. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Acked-by: Javier Martinez Canillas <javier@osg.samsung.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Chanwoo Choi authored
This patch add the cooling device to control the overheating issue on Exynos3250-based Rinato/Monk board. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Chanho Park authored
The odroid-xu3 board which is based on exynos5422 not exynos5800 is booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are cortex-a15 cores. To correct this mis-odering, I added exynos5422-cpus.dtsi and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and cpu4-7 are cortex-a15. Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Chanho Park <parkch98@gmail.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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