- Nov 16, 2016
-
-
Andy Yan authored
RK1108 EVB is designed by Rockchip for CVR field. This patch add basic support for it, which can boot with initramfs into shell. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Andy Yan authored
RK1108 is embedded with an ARM Cortex-A7 single core and a DSP core. It is designed for varies application scenario such as car DVR, sports DV, secure camera and UAV camera. This patch add basic support for it with DMAC / UART / CRU / pinctrl / MMC enabled. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Tested-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Nov 14, 2016
-
-
Paweł Jarosz authored
DMA controller driver is in good shape these days on rockchip platforms. So lets enable DMA for uart and mmc. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Paweł Jarosz authored
This patch fixes incorectly assigned rk3066a TSADC node Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Nov 09, 2016
-
-
Jaehoon Chung authored
In drivers/mmc/core/host.c, there is "max-frequency" property. It should be same behavior. So use the "max-frequency" instead of "clock-freq-min-max". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Nov 06, 2016
-
-
Paweł Jarosz authored
Currently driver leaves sdmmc frequency at its default. So lets set this to 50MHz. This gives us performance boost in mmc transfers. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Oct 22, 2016
-
-
Andy Yan authored
Use definition in rockchip pinctrl header to describe gpios, this will make it more clear. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Paweł Jarosz authored
MK808 is a tv stick which has rockchip rk3066 CPU inside, two usb ports - host and otg, micro sd card slot and onboard wifi RK901. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chip.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Oct 21, 2016
-
-
Paweł Jarosz authored
Initialize PLL, cpu bus and peripherial bus rate while kernel init. No other module does than. This gives us performance boost observable for example in mmc transfers. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Oct 16, 2016
-
-
Shawn Lin authored
Enable these two modes to speed up the booting and improve the performance. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Shawn Lin authored
PopMetal-RK3288 board could enable SD3.0 card but need vccio_sd to support the voltage range from 1V8 to 3V3 and we also need to add more UHS mode here. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Shawn Lin authored
Please don't add these for vcc_sd, and mmc-core/driver will control it. Otherwise, it will waste energy even without sdmmc in slot. Moreover, it will causes a bug: If we insert/remove sd card, we could see [9.337271] mmc0: new ultra high speed SDR25 SDHC card at address 0007 [9.345144] mmcblk0: mmc0:0007 SD32G 29.3 GiB This is okay for normal sd insert/remove test, but when I debug some issues for sdmmc, I did unbind/bind test. And there is a interesting phenomenon when we bind the driver again: [58.314069] mmc0: new high speed SDHC card at address 0007 [58.320282] mmcblk0: mmc0:0007 SD32G 29.3 GiB So the sd card could just support high speed without power cycle since the vcc_sd is always on, which makes the sd card fail to reinit its internal ocr mask. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Finley Xiao authored
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Andy Yan authored
PX3 EVB is designed by Rockchip for automotive field, with integrated CVBS (TP2825) / MIPI DSI / LVDS / HDMI video input/output interface, WIFI/BT/GPS (on a module named S500 which based on MT6620), Gsensor BMA250E and light&proximity sensor STK3410. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Javier Martinez Canillas authored
This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Javier Martinez Canillas authored
This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Javier Martinez Canillas authored
This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Javier Martinez Canillas authored
This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Javier Martinez Canillas authored
The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same, besides empty chosen nodes being removed. So the change should not have a functional impact. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Javier Martinez Canillas authored
The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same, besides empty chosen nodes being removed. So the change should not have a functional impact. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Javier Martinez Canillas authored
The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same, besides empty chosen nodes being removed. So the change should not have a functional impact. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Javier Martinez Canillas authored
The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same, besides empty chosen nodes being removed. So the change should not have a functional impact. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Oct 03, 2016
-
-
Vladimir Zapolskiy authored
The change adds a new device node with description of generic SRAM on-chip memory found on NXP LPC32xx SoC series and connected to AHB matrix slave port 3. Note that NXP LPC3220 SoC has 128KiB of SRAM memory, the other LPC3230, LPC3240 and LPC3250 SoCs all have 256KiB SRAM space, in the shared DTSI file this change specifies 128KiB SRAM size. Also it's worth to mention that the SRAM area contains of 64KiB banks, 2 banks on LPC3220 and 4 banks on the other SoCs from the series, and all SRAM banks but the first one have independent power controls, the description of this feature will be added with the introduction of power domains for the SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
-
- Sep 29, 2016
-
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /soc has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /soc has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /soc has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
As noted in [1], "there are a number of problems with skeleton.dtsi, and it would be prefereable to remove it entirely." This patch is to remove skeleton.dtsi inclusion from berlin2. [1] http://www.spinics.net/lists/arm-kernel/msg528080.html Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
As noted in [1], "there are a number of problems with skeleton.dtsi, and it would be prefereable to remove it entirely." This patch is to remove skeleton.dtsi inclusion from berlin2cd. [1] http://www.spinics.net/lists/arm-kernel/msg528080.html Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
As noted in [1], "there are a number of problems with skeleton.dtsi, and it would be prefereable to remove it entirely." This patch is to remove skeleton.dtsi inclusion from berlin2q. [1] http://www.spinics.net/lists/arm-kernel/msg528080.html Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
After commit f29a72c2 ("watchdog: dw_wdt: Convert to use watchdog infrastructure"), the dw_wdt driver can support multiple variants, so unconditionally enable all dw_wdt nodes now. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
After commit f29a72c2 ("watchdog: dw_wdt: Convert to use watchdog infrastructure"), the dw_wdt driver can support multiple variants, so unconditionally enable all dw_wdt nodes now. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
- Sep 27, 2016
-
-
Wei Ni authored
Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
-
Wei Ni authored
Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones for all Tegra124 platform, these trips can trigger shut down or reset. Tegra124 Jetson TK1 was already set "critical" trips before, so it can overwrite the general values. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
-
Hans de Goede authored
Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i and newer. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-
- Sep 21, 2016
-
-
Alexandre TORGUE authored
Originally-from: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: arnd@arndb.de Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: bruherrera@gmail.com Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: lee.jones@linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1474387259-18926-5-git-send-email-alexandre.torgue@st.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-
Hans de Goede authored
Add a dt node describing the mma7660 accelerometer on the polaroid-mid2407pxe03 tablet. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-
Icenowy Zheng authored
UART1 is connected to the bluetooth part of RTL8723BS WiFi/BT combo card on iNet D978 Rev2 board. Enable the UART1 to make it possible to use the modified hciattach by Realtek to drive the BT part of RTL8723BS. On the board no r_uart pins are found now (the onboard RX/TX pins are wired to PF2/PF4, which is muxed with mmc0), so also disabled it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-