The Olimex A20-Olinuxino is an open-hardware board based on the
Allwinner A20 SoC, with most of the pins exported on headers, a 10/100M
ethernet port, SATA, SD and uSD slots, etc.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The Allwinner A20 SoC is based on 2 Cortex A7, an ARM Mali GPU, and is
built to be pin-compatible with the older Allwinner A10.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

This platform from WITS is the evaluation board for the Allwinner A31.
It features a quad-Cortex A7, 2048MB of RAM, NAND, USB, MMC, several
UART, HDMI, a 2048 x 1536 10" screen, powered by a PowerVR, etc.

Of course, most of these peripherals aren't supported yet, but support
for those will come eventually.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The Allwinner A31 SoC is a multimedia SoC powered by 4 Cortex-A7 and a
PowerVR GPU.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

This adds a device tree usable on Mele A1000 (and A2000, as it
apparently is the same device except for the case). This device features
one UART port, Ethernet, an AXP209 PMU on i2c0 and two user configurable
LEDs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
[maxime: fixed the soc node address]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

There was a typo in the base address used for the soc node in the A13
device tree. Fix it with the proper base address.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The reg property of the simple-bus driver is completely useless. Remove
it from the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

There was a typo in the base address used for the soc node in the A10s
device tree. Fix it with the proper base address.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The reg property of the simple-bus driver is completely useless. Remove
it from the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

There was a typo in the base address used for the soc node in the A10
device tree. Fix it with the proper base address.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The reg property of the simple-bus driver is completely useless. Remove
it from the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Quoting from Documentation/leds/leds-class.txt:

    LED Device Naming
    =================

    Is currently of the form:

    "devicename:colour:function"

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

This OLIMEX board has a AT24C16BN-SH EEPROM holding the MAC address.
This patch adds the corresponding device tree node to reflect this.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

This board from OLIMEX is using the three I2C controllers present on A10S:
  * I2C-0 connects to the AXP152 PMU
  * I2C-1 holds an AT24C16BN-SH EEPROM with the MAC address for ethernet
  * I2C-2 is used for UEXT modules.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Allwinner A10S has 3 I2C controllers embedded on it. Add them to the
corresponding dtsi.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The information has been extracted from the A10S-OLinuXino-Micro
schematics, as we do not have a user manual for A10S yet.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Integrates the LZ4 decompression code to the arm pre-boot code.

Signed-off-by: Kyungsik Lee <kyungsik.lee@lge.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Yann Collet <yann.collet.73@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

On CSR SiRFprimaII/atlasVI, there is a programmable 16-bit divider
(RTC_DIV) that divides the input 32.768KHz clock to the frequency that
users need (E.g.  1 Hz).  The divided real-time clock will be used to
drive a 32-bit counter (RTC_COUNTER) that provides users with the actual
time.

In each cycle of the divided real-time clock, there is a Hertz interrupt
generated to the RISC.  Users can also configure an alarm (RTC_ALARM).
When RTC_COUNTER matches the alarm, there will be an alarm interrupt
generated to the RISC.

The system RTC can generate an alarm wake-up signal to notify the power
controller to wake up from power saving mode.

Signed-off-by: Xianglong Du <Xianglong.Du@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Commit 4c94c8b5 "ARM: tegra: update device trees for USB binding rework"
added regulator definitions for GPIO-controlled USB VBUS. However, none
of these contained the essential DT property enable-active-high. Add
this so that the regulator definitions are correct.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This patch renames the combatible strings for hdmi, mixer, ddc
and hdmiphy. It follows the convention of using compatible string
which represent the SoC in which the IP was added for the first
time.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

Several drivers need font support independent of CONFIG_VT, cfr. commit
9cbce8d7e1dae0744ca4f68d62aa7de18196b6f4, "console/font: Refactor font
support code selection logic").
Hence move the fonts and their support logic from drivers/video/console/ to
its own library directory lib/fonts/.
This also allows to limit processing of drivers/video/console/Makefile to
CONFIG_VT=y again.

[Kevin Hilman <khilman@linaro.org>: Update arch/arm/boot/compressed/Makefile]
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>

Instead of using a GPIO to turn on/off the CAN transceiver, it is better to
use a regulator as some systems may use a PMIC to power the CAN transceiver.

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

This alters the local side address of the iospace to zero,
non prefetchable memory local side address to 0x00000000 and
prefetchable memory local side address to 0x10000000,
so as to match the values actually poked in by the driver.

Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

function-mask DT property is now a mask for a pin at each pin offset
inside a given pincontrol register. Fix DA850 DT data to reflect
this change.

Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
[nsekhar@ti.com: reword commit message for clarity]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

This patch adds pcie controller node for exynos5440-ssdk5440,
and also adds a phandle for pin controller node.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Exynos5440 has two PCIe controllers which can be used as root complex
for PCIe interface.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Wenyou Yang <wenyou.yang@atmel.com>

In previous version of SPI driver we where using different compatibility stings
for finding SPI features. We are now using the IP revision information.
So we stay with the unique compatibility string for this driver:
"atmel,at91rm9200-spi".

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Wenyou Yang <wenyou.yang@atmel.com>

B2020 ADI board is reference board for STIH415/416 SOCs, it has 2 x
UART, 4x USB, 1 x Ethernet, 1 x SATA, 1 x PCIe, and 2GB RAM  with
standard set-top box IPs.

This patch adds initial support to B2020 with STiH415/416 with SBC_UART1
as console and a heard beat LED.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
CC: Stephen Gallimore <stephen.gallimore@st.com>
CC: Stuart Menefy <stuart.menefy@st.com>
CC: Arnd Bergmann <arnd@arndb.de>

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.

This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
CC: Stephen Gallimore <stephen.gallimore@st.com>
CC: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>

The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
CC: Stephen Gallimore <stephen.gallimore@st.com>
CC: Stuart Menefy <stuart.menefy@st.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Linus Walleij <linus.walleij@linaro.org>

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
1.0 GHz, dual-core CPU.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
CC: Stephen Gallimore <stephen.gallimore@st.com>
CC: Stuart Menefy <stuart.menefy@st.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

arm26 support in Linux is long gone, yet it left an interresting,
fossilized trace in the decompressor.

Remove it so people won't get confused about what teqp is actually
doing here...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

The length of the registers area for the Marvell 370/XP Ethernet controller
was incorrect in the .dtsi: 0x2500, while it should have been 0x4000.
This problem wasn't noticed because there used to be a static mapping for
all the MMIO register region set up by ->map_io().

The register length was fixed in all the other device tree files,
except from the armada-xp-mv78260.dtsi, in the following commit:

  commit cf8088c5
  Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  Date:   Tue May 21 12:33:27 2013 +0200

    arm: mvebu: fix length of Ethernet registers area in .dtsi

This commit fixes a kernel panic in mvneta_probe(), when the kernel
tries to access the unmapped registers:

[  163.639092] mvneta d0070000.ethernet eth0: mac: 6e:3c:4f:87:17:2e
[  163.646962] mvneta d0074000.ethernet eth1: mac: 6a:04:4e:6f:f5:ef
[  163.654853] mvneta d0030000.ethernet eth2: mac: 2a:99:19:19:fc:4c
[  163.661258] Unable to handle kernel paging request at virtual address f011bcf0
[  163.668523] pgd = c0004000
[  163.671237] [f011bcf0] *pgd=2f006811, *pte=00000000, *ppte=00000000
[  163.677565] Internal error: Oops: 807 [#1] SMP ARM
[  163.682370] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc6-01850-gba0682e #11
[  163.690046] task: ef04c000 ti: ef03e000 task.ti: ef03e000
[  163.695467] PC is at mvneta_probe+0x34c/0xabc
[...]

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

This patch adds device trees for describing the TI-Nspire hardware.

Changes between v1 and v2:
* Change "keymap" binding to the standard "linux,keymap" binding.

Signed-off-by: Daniel Tang <dt.tangr@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Although the internal register window size is 1 MiB, the previous
ranges translation for the internal register space had a size of
0x4000000. This was done to allow the crypto and nand node to access
the corresponding 'sram' and 'nand' decoding windows.

In order to describe the hardware more accurately, we declare the
real 1 MiB internal register space in the ranges, and add a translation
entry for the nand node to access the 'nand' window.

This commit will make future improvements on the MBus DT binding easier.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

When this node was added, the AB8500 GPIO driver was pretty broken.
As a hack, we pretended that NOMADIK GPIO 26 was the correct on/off
pin, as it was unused. It worked because AB8500 GPIO 26 was in an
'always on from boot' state. Now the AB8500 GPIO driver is working,
the default state for all the pins is 'off'. Let's flip back over to
use the correct GPIO which is _actually_ attached to the regulator.

We're also taking the opportunity to straighten out some formatting
misdemeanours, swapping spaces for tabs.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>