- Jan 24, 2017
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Jagan Teki authored
Engicam Is.IoT MX6UL has separate module for eMMC, so add emmc dts file for imx6ul-isiot.dtsi, usdhc2 node represent eMMC. dmesg: ----- mmc1: SDHCI controller on 2194000.usdhc [2194000.usdhc] using ADMA mmc1: new DDR MMC card at address 0001 mmcblk1: mmc1:0001 M62704 3.53 GiB Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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- Jan 23, 2017
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Jagan Teki authored
Fixed code indent tabs in respective imx6qdl dtsi files and also add space on imx6qdl-icore-rqs.dtsi on usdhc bus-width nodes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Vivien Didelot authored
The ZII Dev Rev C board has EEPROMs hanging the 88E6390 Ethernet switch chips. Add an "eeprom-length" property to allow access from ethtool. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Sébastien Szymanski authored
OPOS6UL is an i.MX6UL based SoM. OPOS6ULDev is a carrier board for the OPOS6UL SoM. For more details see: http://www.opossom.com/english/products-processor_boards-opos6ul.html http://www.opossom.com/english/products-development_boards-opos6ul_dev.html Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
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Christopher Spinrath authored
Apart from the already enabled Designware HDMI port, the Utilite Pro has a second display pipeline which has the following shape: IPU1 DI0 --> Parallel display --> tfp410 rgb24 to DVI encoder --> HDMI connector. Enable support for it. In addition, since this pipeline is hardwired to IPU1, sever the link between IPU1 and the SoC-internal Designware HDMI encoder forcing the latter to be connected to IPU2 instead of IPU1. Otherwise, it is not possible to drive both displays at high resolution due to the bandwidth limitations of a single IPU. Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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- Jan 10, 2017
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Andrey Smirnov authored
Add .dts file for rev. C of the board by factoring out commonalities into a shared include file (vf610-zii-dev-rev-b-c.dtsi) and deriving revision specific file from it (vf610-zii-dev-rev-b.dts and vf610-zii-dev-reb-c.dts). Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stefan Agner <stefan@agner.ch> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: andrew@lunn.ch Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Cc: cphealy@gmail.com Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Andrey Smirnov authored
Remove pwm0grp since it is: a) Not referenced anywhere in the DTS file (unlike Tower board it is based on, this board does not use/expose FTM0) b) Configures PTB2 and PTB3 in a way that contradicts pinctrl-mdio-mux Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stefan Agner <stefan@agner.ch> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: andrew@lunn.ch Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Cc: cphealy@gmail.com Tested-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Milo Kim authored
Use common board file and support SATA interface additionally. Specify the dtb file for i.MX6 build. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Milo Kim authored
Common savageboard DT file is used for board support. Add the vendor name and specify the dtb file for i.MX6Q build. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Milo Kim authored
* Memory memblock for DDR3 1GB * Regulator 3.3V for panel and backlight. * Display Enable HDMI and LVDS panel. Savageboard supports AVIC TM097TDH02 panel which is compatible with Hannstar HSD100PXN1, so reuse it. * Clock The commit d28be499 ("ARM: dts: imx6qdl-sabresd: Allow HDMI and LVDS to work simultaneously") is applied to support LVDS and HDMI output at the same time. * Pinmux Support eMMC, ethernet, gpio key for power button, I2C, PWM, SD card and UART. * Others Enable ethernet, UART1 debug, USB host, USDHC3 for microSD card and USDHC4 for built-in eMMC storage. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Fabio Estevam authored
On imx53-qsb the TVE DAC regulator comes from: - LDO7 on the board with the Dialog DA9052 PMIC - VDAC on the board with the MC34708 PMIC Pass them in the 'dac-supply' node. While at it, remove the 'regulator-always-on/regulator-boot-on' properties as the TVE driver will properly handle it. Tested on a imx53-qsb board with a Dialog DA9052 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Lukasz Majewski authored
This patch provides support for Liebherr's Monitor 6 board (abverrated as mccmon6) to Linux kernel. Signed-off-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Alexandre Belloni authored
The license text has been mangled at some point then copy pasted across multiple files. Restore it to what it should be. Note that this is not intended as a license change. Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Afzal Mohammed <afzal.mohd.ma@gmail.com> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Martin Kaiser authored
The DryIce block on i.MX25 chipset uses two interrupts: A normal and a security violation interrupt. Add the security violation interrupt to the list, it is optional. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Bai Ping authored
Add ocotp node for i.MX6UL SOC. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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- Jan 03, 2017
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Jagan Teki authored
Is.IoT MX6UL modules are system on module solutions manufactured by Engicam for IOT connectivity applications with following characteristics: CPU NXP i.MX6UL (G2) Cortex-A7@528 MHz RAM Up to 512 MB LvDDR3@800MT/s NAND 256MB (option) eMMC 4GB (option) LCD 18 bit parallel BT 2.1+EDR,Bluetooth 3.0, Bluetooth 4.1 (Bluetooth low energy) WLAN IEEE 802.11 b/g/n (single stream n) Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Jagan Teki authored
Engicam i.CoreM6 Dual and Quad SOM's use same dts file, hence update model name to add Dual and also added full mode decsription. Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Jagan Teki authored
i.CoreM6 DualLite/Solo modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DL, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066 NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD and more info at http://www.engicam.com/en/products/embedded/som/standard/i-core-rqs-m6s-dl-d-q Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Fabio Estevam authored
Property 'anatop-enable-bit' does not exist, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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- Jan 02, 2017
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Vladimir Zapolskiy authored
Since commit b36581df ("spi: imx: Using existing properties for chipselects") the device tree property 'fsl,spi-num-chipselects' is unused and it is already marked as obsolete in device tree binding documentation. Remove the property from the existing DTS files to avoid its reoccurence on copying. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Jörg Krause authored
Add simple-card support to SAIF0 and SAIF1. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Fabio Estevam authored
imx6sx-udoo-neo has a KSZ8091 Ethernet PHY, which requires the reset signal to be low for at least 10ms. Pass the 'phy-reset-duration' property to reflect such requirement. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Gary Bisson authored
The bus format is therefore retrieved from the connected panel information. Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Christopher Spinrath authored
Enable the S/PDIF transceiver present on the cm-fx6 module. Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Tim Harvey authored
All of the Gateworks Ventana boards based on the IMX6 SoC except for the GW54xx use the LTC3676 PMIC. Add a device-tree node with interrupt support for this PMIC. Additionally remove the simple-bus notation in the regulator nodes and any fixed regulators that are provided by the PMIC. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Tim Harvey authored
The GW54xx revision E adds SPI via an off-board connector. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Fabio Estevam authored
Make CPU nodes consistent throughout the i.MX dts files, which also matches the description from ePAPR spec. This also fixes the following W=1 warning in some cases: Warning (unit_address_vs_reg): Node /cpus/cpu@0 has a unit name, but no reg property Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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- Dec 30, 2016
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Linus Torvalds authored
In commit 62906027 ("mm: add PageWaiters indicating tasks are waiting for a page bit") Nick Piggin made our page locking no longer unconditionally touch the hashed page waitqueue, which not only helps performance in general, but is particularly helpful on NUMA machines where the hashed wait queues can bounce around a lot. However, the "clear lock bit atomically and then test the waiters bit" sequence turns out to be much more expensive than it needs to be, because you get a nasty stall when trying to access the same word that just got updated atomically. On architectures where locking is done with LL/SC, this would be trivial to fix with a new primitive that clears one bit and tests another atomically, but that ends up not working on x86, where the only atomic operations that return the result end up being cmpxchg and xadd. The atomic bit operations return the old value of the same bit we changed, not the value of an unrelated bit. On x86, we could put the lock bit in the high bit of the byte, and use "xadd" with that bit (where the overflow ends up not touching other bits), and look at the other bits of the result. However, an even simpler model is to just use a regular atomic "and" to clear the lock bit, and then the sign bit in eflags will indicate the resulting state of the unrelated bit #7. So by moving the PageWaiters bit up to bit #7, we can atomically clear the lock bit and test the waiters bit on x86 too. And architectures with LL/SC (which is all the usual RISC suspects), the particular bit doesn't matter, so they are fine with this approach too. This avoids the extra access to the same atomic word, and thus avoids the costly stall at page unlock time. The only downside is that the interface ends up being a bit odd and specialized: clear a bit in a byte, and test the sign bit. Nick doesn't love the resulting name of the new primitive, but I'd rather make the name be descriptive and very clear about the limitation imposed by trying to work across all relevant architectures than make it be some generic thing that doesn't make the odd semantics explicit. So this introduces the new architecture primitive clear_bit_unlock_is_negative_byte(); and adds the trivial implementation for x86. We have a generic non-optimized fallback (that just does a "clear_bit()"+"test_bit(7)" combination) which can be overridden by any architecture that can do better. According to Nick, Power has the same hickup x86 has, for example, but some other architectures may not even care. All these optimizations mean that my page locking stress-test (which is just executing a lot of small short-lived shell scripts: "make test" in the git source tree) no longer makes our page locking look horribly bad. Before all these optimizations, just the unlock_page() costs were just over 3% of all CPU overhead on "make test". After this, it's down to 0.66%, so just a quarter of the cost it used to be. (The difference on NUMA is bigger, but there this micro-optimization is likely less noticeable, since the big issue on NUMA was not the accesses to 'struct page', but the waitqueue accesses that were already removed by Nick's earlier commit). Acked-by: Nick Piggin <npiggin@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Bob Peterson <rpeterso@redhat.com> Cc: Steven Whitehouse <swhiteho@redhat.com> Cc: Andrew Lutomirski <luto@kernel.org> Cc: Andreas Gruenbacher <agruenba@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Mel Gorman <mgorman@techsingularity.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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- Dec 27, 2016
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Thomas Gleixner authored
If mce_device_init() fails then the mce device pointer is NULL and the AMD mce code happily dereferences it. Add a sanity check. Reported-by: Markus Trippelsdorf <markus@trippelsdorf.de> Reported-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Al Viro authored
Split asm-only parts of arm64 uaccess.h into a new header and use that from *.S. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
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- Dec 26, 2016
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Larry Finger authored
I am getting the following warning when I build kernel 4.9-git on my PowerBook G4 with a 32-bit PPC processor: AS arch/powerpc/kernel/misc_32.o arch/powerpc/kernel/misc_32.S:299:7: warning: "CONFIG_FSL_BOOKE" is not defined [-Wundef] This problem is evident after commit 989cea5c ("kbuild: prevent lib-ksyms.o rebuilds"); however, this change in kbuild only exposes an error that has been in the code since 2005 when this source file was created. That was with commit 9994a338 ("powerpc: Introduce entry_{32,64}.S, misc_{32,64}.S, systbl.S"). The offending line does not make a lot of sense. This error does not seem to cause any errors in the executable, thus I am not recommending that it be applied to any stable versions. Thanks to Nicholas Piggin for suggesting this solution. Fixes: 9994a338 ("powerpc: Introduce entry_{32,64}.S, misc_{32,64}.S, systbl.S") Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Thomas Gleixner authored
ktime_set(S,N) was required for the timespec storage type and is still useful for situations where a Seconds and Nanoseconds part of a time value needs to be converted. For anything where the Seconds argument is 0, this is pointless and can be replaced with a simple assignment. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org>
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- Dec 25, 2016
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Thomas Gleixner authored
There is no point in having an extra type for extra confusion. u64 is unambiguous. Conversion was done with the following coccinelle script: @rem@ @@ -typedef u64 cycle_t; @fix@ typedef cycle_t; @@ -cycle_t +u64 Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: John Stultz <john.stultz@linaro.org>
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Thomas Gleixner authored
When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen. Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sebastian Siewior <bigeasy@linutronix.de> Link: http://lkml.kernel.org/r/20161221192112.085444152@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Thomas Gleixner authored
The error cleanup which is invoked when the hotplug state setup failed tries to remove the failed state, which is broken. Fixes: 8fba38c9 ("x86/msr: Convert to hotplug state machine") Reported-by: kernel test robot <fengguang.wu@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Sebastian Siewior <bigeasy@linutronix.de>
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Thomas Gleixner authored
If the pmu registration fails the registered hotplug callbacks are not removed. Wrong in any case, but fatal in case of a modular driver. Replace the nonsensical state names with proper ones while at it. Fixes: 77c34ef1 ("perf/x86/intel/cstate: Convert Intel CSTATE to hotplug state machine") Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Sebastian Siewior <bigeasy@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: stable@vger.kernel.org
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Thomas Gleixner authored
The cpu hotplug support of this perf driver is broken in several ways: 1) It adds a instance before setting up the state. 2) The state for the instance is different from the state of the callback. It's just a randomly chosen state. 3) The instance registration is not error checked so nobody noticed that the call can never succeed. 4) The state for the multi install callbacks is chosen randomly and overwrites existing state. This is now prevented by the core code so the call is guaranteed to fail. 5) The error exit path in the init function leaves the instance registered and then frees the memory which contains the enqueued hlist node. 6) The remove function is removing the state and not the instance. Fix it by: - Setting up the state before adding instances. Use a dynamically allocated state for it. - Installing instances after the state has been set up - Removing the instance in the error path before freeing memory - Removing the instance not the state in the driver remove callback While at is use raw_cpu_processor_id(), because cpu_processor_id() cannot be used in preemptible context, and set the driver data after successful registration of the pmu. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sebastian Siewior <bigeasy@linutronix.de> Cc: Frank Li <frank.li@nxp.com> Cc: Zhengyu Shen <zhengyu.shen@nxp.com> Link: http://lkml.kernel.org/r/20161221192111.596204211@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Linus Torvalds authored
This was entirely automated, using the script by Al: PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*<asm/uaccess.h>' sed -i -e "s!$PATT!#include <linux/uaccess.h>!" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h) to do the replacement at the end of the merge window. Requested-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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- Dec 24, 2016
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Josh Poimboeuf authored
Revert the following commit: b6959a36 ("x86/unwind: Detect bad stack return address") ... because Andrey Konovalov reported an unwinder warning: WARNING: unrecognized kernel stack return address ffffffffa0000001 at ffff88006377fa18 in a.out:4467 The unwind was initiated from an interrupt which occurred while running in the generated code for a kprobe. The unwinder printed the warning because it expected regs->ip to point to a valid text address, but instead it pointed to the generated code. Eventually we may want come up with a way to identify generated kprobe code so the unwinder can know that it's a valid return address. Until then, just remove the warning. Reported-by: Andrey Konovalov <andreyknvl@google.com> Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Masami Hiramatsu <mhiramat@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/02f296848fbf49fb72dfeea706413ecbd9d4caf6.1482418739.git.jpoimboe@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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- Dec 23, 2016
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Peter Zijlstra authored
Jiri reported the overlap scheduling exceeding its max stack. Looking at the constraint that triggered this, it turns out the overlap marker isn't needed. The comment with EVENT_CONSTRAINT_OVERLAP states: "This is the case if the counter mask of such an event is not a subset of any other counter mask of a constraint with an equal or higher weight". Esp. that latter part is of interest here I think, our overlapping mask is 0x0e, that has 3 bits set and is the highest weight mask in on the PMU, therefore it will be placed last. Can we still create a scenario where we would need to rewind that? The scenario for AMD Fam15h is we're having masks like: 0x3F -- 111111 0x38 -- 111000 0x07 -- 000111 0x09 -- 001001 And we mark 0x09 as overlapping, because it is not a direct subset of 0x38 or 0x07 and has less weight than either of those. This means we'll first try and place the 0x09 event, then try and place 0x38/0x07 events. Now imagine we have: 3 * 0x07 + 0x09 and the initial pick for the 0x09 event is counter 0, then we'll fail to place all 0x07 events. So we'll pop back, try counter 4 for the 0x09 event, and then re-try all 0x07 events, which will now work. The masks on the PMU in question are: 0x01 - 0001 0x03 - 0011 0x0e - 1110 0x0c - 1100 But since all the masks that have overlap (0xe -> {0xc,0x3}) and (0x3 -> 0x1) are of heavier weight, it should all work out. Reported-by: Jiri Olsa <jolsa@kernel.org> Tested-by: Jiri Olsa <jolsa@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Liang Kan <kan.liang@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Robert Richter <rric@kernel.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vince@deater.net> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: http://lkml.kernel.org/r/20161109155153.GQ3142@twins.programming.kicks-ass.net Signed-off-by: Ingo Molnar <mingo@kernel.org>
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