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    • James Hartley's avatar
      MIPS: pistachio: Determine SoC revision during boot · ae07ea85
      James Hartley authored 
      

Now that there are different revisions of the Pistachio SoC
in circulation, add this information to the boot log to make
it easier for users to determine which hardware they have.

Signed-off-by: default avatarJames Hartley <james.hartley@imgtec.com>
Signed-off-by: default avatarIonela Voinescu <ionela.voinescu@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13130/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      ae07ea85
    • Florian Fainelli's avatar
      MIPS: BMIPS: Adjust mips-hpt-frequency for BCM7435 · 80fa40ac
      Florian Fainelli authored 
      

The CPU actually runs at 1405Mhz which gives us a 175625000 Hz MIPS timer
frequency (CPU frequency / 8).

Fixes: e4c7d009 ("MIPS: BMIPS: Add BCM7435 dtsi")
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jaedon.shin@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/13132/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      80fa40ac
    • Sashka Nochkin's avatar
      mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type · 86ce9a34
      Sashka Nochkin authored 
      

Mediatek MT7620 SoC has syscfg0 bits where it sets the type of memory being used.
However, sometimes those bits are not set properly (reading "11"). In this case, the SoC assumes SDRAM.
The patch below reflects that.

Signed-off-by: default avatarSashka Nochkin <linux-mips@durdom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13135/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      86ce9a34
    • Paul Burton's avatar
      MIPS: Prevent "restoration" of MSA context in non-MSA kernels · 6533af4d
      Paul Burton authored 
      

If a kernel doesn't support MSA context (ie. CONFIG_CPU_HAS_MSA=n) then
it will only keep 64 bits per FP register in thread context, and the
calls to set_fpr64 in restore_msa_extcontext will overrun the end of the
FP register context into the FCSR & MSACSR values. GCC 6.x has become
smart enough to detect this & complain like so:

    arch/mips/kernel/signal.c: In function 'protected_restore_fp_context':
    ./arch/mips/include/asm/processor.h:114:17: error: array subscript is above array bounds [-Werror=array-bounds]
      fpr->val##width[FPR_IDX(width, idx)] = val;   \
      ~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~
    ./arch/mips/include/asm/processor.h:118:1: note: in expansion of macro 'BUILD_FPR_ACCESS'
     BUILD_FPR_ACCESS(64)

The only way to trigger this code to run would be for a program to set
up an artificial extended MSA context structure following a sigframe &
execute sigreturn. Whilst this doesn't allow a program to write to any
state that it couldn't already, it makes little sense to allow this
"restoration" of MSA context in a system that doesn't support MSA.

Fix this by killing a program with SIGSYS if it tries something as crazy
as "restoring" fake MSA context in this way, also fixing the build error
& allowing for most of restore_msa_extcontext to be optimised out of
kernels without support for MSA.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Reported-by: default avatarMichal Toman <michal.toman@imgtec.com>
Fixes: bf82cb30 ("MIPS: Save MSA extended context around signals")
Tested-by: default avatarAaro Koskinen <aaro.koskinen@iki.fi>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Michal Toman <michal.toman@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: stable <stable@vger.kernel.org> # v4.3+
Patchwork: https://patchwork.linux-mips.org/patch/13164/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      6533af4d
    • James Hogan's avatar
      MIPS: cevt-r4k: Dynamically calculate min_delta_ns · 1fa40555
      James Hogan authored 
      

Calculate the MIPS clockevent device's min_delta_ns dynamically based on
the time it takes to perform the mips_next_event() sequence.

Virtualisation in particular makes the current fixed min_delta of 0x300
inappropriate under some circumstances, as the CP0_Count and CP0_Compare
registers may be being emulated by the hypervisor, and the frequency may
not correspond directly to the CPU frequency.

We actually use twice the median of multiple 75th percentiles of
multiple measurements of how long the mips_next_event() sequence takes,
in order to fairly efficiently eliminate outliers due to unexpected
hypervisor latency (which would need handling with retries when it
occurs during normal operation anyway).

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13176/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      1fa40555
    • James Hogan's avatar
      MIPS: malta-time: Take seconds into account · 24e1df66
      James Hogan authored 
      

When estimating the clock frequency based on the RTC, take seconds into
account in case the Update In Progress (UIP) bit wasn't seen. This can
happen in virtual machines (which may get pre-empted by the hypervisor
at inopportune times) with QEMU emulating the RTC (and in fact not
setting the UIP bit for very long), especially on slow hosts such as
FPGA systems and hardware emulators. This results in several seconds
actually having elapsed before seeing the UIP bit instead of just one
second, and exaggerated timer frequencies.

While updating the comments, they're also fixed to match the code in
that the rising edge of the update flag is detected first, not the
falling edge.

The rising edge gives a more precise point to read the counters in a
virtualised system than the falling edge, resulting in a more accurate
frequency.

It does however mean that we have to also wait for the falling edge
before doing the read of the RTC seconds register, otherwise it seems to
be possible in slow hardware emulation to stray into the interval when
the RTC time is undefined during the update (at least 244uS after the
rising edge of the update flag). This can result in both seconds values
reading the same, and it wrapping to 60 seconds, vastly underestimating
the frequency.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13174/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      24e1df66