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  1. Sep 09, 2014
  2. Sep 01, 2014
    • Guenter Roeck's avatar
      unicore32: Fix build error · ca98565a
      Guenter Roeck authored
      unicore32 builds fail with
      
        arch/unicore32/kernel/signal.c: In function ‘setup_frame’:
        arch/unicore32/kernel/signal.c:257: error: ‘usig’ undeclared (first use in this function)
        arch/unicore32/kernel/signal.c:279: error: ‘usig’ undeclared (first use in this function)
        arch/unicore32/kernel/signal.c: In function ‘handle_signal’:
        arch/unicore32/kernel/signal.c:306: warning: unused variable ‘tsk’
        arch/unicore32/kernel/signal.c: In function ‘do_signal’:
        arch/unicore32/kernel/signal.c:376: error: implicit declaration of function ‘get_signsl’
        make[1]: *** [arch/unicore32/kernel/signal.o] Error 1
        make: *** [arch/unicore32/kernel/signal.o] Error 2
      
      Bisect points to commit 649671c9 ("unicore32: Use get_signal()
      signal_setup_done()").
      
      This code never even compiled.  Reverting the patch does not work, since
      previously used functions no longer exist, so try to fix it up.  Compile
      tested only.
      
      Fixes: 649671c9
      
       ("unicore32: Use get_signal() signal_setup_done()")
      Cc: Richard Weinberger <richard@nod.at>
      Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      ca98565a
    • Alex Shi's avatar
      vexpress/spc: fix a build warning on array bounds · e160cc17
      Alex Shi authored
      
      
      With ARCH_VEXPRESS_SPC option, kernel build has the following
      warning:
      
      arch/arm/mach-vexpress/spc.c: In function ‘ve_spc_clk_init’:
      arch/arm/mach-vexpress/spc.c:431:38: warning: array subscript is below array bounds [-Warray-bounds]
        struct ve_spc_opp *opps = info->opps[cluster];
                                            ^
      since 'cluster' maybe '-1' in UP system. This patch does a active
      checking to fix this issue.
      
      Signed-off-by: default avatarAlex Shi <alex.shi@linaro.org>
      Acked-by: default avatarPawel Moll <pawel.moll@arm.com>
      Acked-by: default avatarSudeep Holla <sudeep.holla@arm.com>
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      e160cc17
  3. Aug 30, 2014
  4. Aug 29, 2014
  5. Aug 28, 2014
  6. Aug 27, 2014
    • Juri Lelli's avatar
      ARM: 8130/1: cpuidle/cpuidle-big_little: fix reading cpu id part number · eba1c718
      Juri Lelli authored
      Commit af040ffc
      
       ("ARM: make it easier to check the CPU part number
      correctly") changed ARM_CPU_PART_X masks, and the way they are returned and
      checked against. Usage of read_cpuid_part_number() is now deprecated, and
      calling places updated accordingly. This actually broke cpuidle-big_little
      initialization, as bl_idle_driver_init() performs a check using an hardcoded
      mask on cpu_id.
      
      Create an interface to perform the check (that is now even easier to read).
      Define also a proper mask (ARM_CPU_PART_MASK) that makes this kind of checks
      cleaner and helps preventing bugs in the future. Update usage accordingly.
      
      Signed-off-by: default avatarJuri Lelli <juri.lelli@arm.com>
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      eba1c718
    • Mark Rutland's avatar
      ARM: 8129/1: errata: work around Cortex-A15 erratum 830321 using dummy strex · 2c32c65e
      Mark Rutland authored
      
      
      On revisions of Cortex-A15 prior to r3p3, a CLREX instruction at PL1 may
      falsely trigger a watchpoint exception, leading to potential data aborts
      during exception return and/or livelock.
      
      This patch resolves the issue in the following ways:
      
        - Replacing our uses of CLREX with a dummy STREX sequence instead (as
          we did for v6 CPUs).
      
        - Removing the clrex code from v7_exit_coherency_flush and derivatives,
          since this only exists as a minor performance improvement when
          non-cached exclusives are in use (Linux doesn't use these).
      
      Benchmarking on a variety of ARM cores revealed no measurable
      performance difference with this change applied, so the change is
      performed unconditionally and no new Kconfig entry is added.
      
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      2c32c65e
    • Mark Rutland's avatar
      ARM: 8128/1: abort: don't clear the exclusive monitors · 85868313
      Mark Rutland authored
      The ARMv6 and ARMv7 early abort handlers clear the exclusive monitors
      upon entry to the kernel, but this is redundant:
      
        - We clear the monitors on every exception return since commit
          200b812d
      
       ("Clear the exclusive monitor when returning from an
          exception"), so this is not necessary to ensure the monitors are
          cleared before returning from a fault handler.
      
        - Any dummy STREX will target a temporary scratch area in memory, and
          may succeed or fail without corrupting useful data. Its status value
          will not be used.
      
        - Any other STREX in the kernel must be preceded by an LDREX, which
          will initialise the monitors consistently and will not depend on the
          earlier state of the monitors.
      
      Therefore we have no reason to care about the initial state of the
      exclusive monitors when a data abort is taken, and clearing the monitors
      prior to exception return (as we already do) is sufficient.
      
      This patch removes the redundant clearing of the exclusive monitors from
      the early abort handlers.
      
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      85868313
    • Andrey Ryabinin's avatar
      ARM: 8127/1: module: add support for R_ARM_TARGET1 relocations · 55f0fb6a
      Andrey Ryabinin authored
      
      
      Kernel module build with GCOV profiling fails to load with the
      following error:
      
       $ insmod test_module.ko
         test_module: unknown relocation: 38
         insmod: can't insert 'test_module.ko': invalid module format
      
      This happens because constructor pointers in the .init_array section
      have not supported R_ARM_TARGET1 relocation type.
      
      Documentation (ELF for the ARM Architecture) says:
          "The relocation must be processed either in the same way as R_ARM_REL32 or
           as R_ARM_ABS32: a virtual platform must specify which method is used."
      
      Since kernel expects to see absolute addresses in .init_array R_ARM_TARGET1
      relocation type should be treated the same way as R_ARM_ABS32.
      
      Signed-off-by: default avatarAndrey Ryabinin <a.ryabinin@samsung.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      55f0fb6a
    • Jiang Liu's avatar
      x86: irq: Fix bug in setting IOAPIC pin attributes · f395dcae
      Jiang Liu authored
      Commit 15a3c7cc
      
       "x86, irq: Introduce two helper functions
      to support irqdomain map operation" breaks LPSS ACPI enumerated
      devices.
      
      On startup, IOAPIC driver preallocates IRQ descriptors and programs
      IOAPIC pins with default level and polarity attributes for all legacy
      IRQs. Later legacy IRQ users may fail to set IOAPIC pin attributes
      if the requested attributes conflicts with the default IOAPIC pin
      attributes. So change mp_irqdomain_map() to allow the first legacy IRQ
      user to reprogram IOAPIC pin with different attributes.
      
      Reported-and-tested-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: default avatarJiang Liu <jiang.liu@linux.intel.com>
      Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Joerg Roedel <joro@8bytes.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Randy Dunlap <rdunlap@infradead.org>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Prarit Bhargava <prarit@redhat.com>
      Link: http://lkml.kernel.org/r/1409118795-17046-1-git-send-email-jiang.liu@linux.intel.com
      
      
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      f395dcae
    • Rabeeh Khoury's avatar
      ARM: dts: microsom-ar8035: MDIO pad must be set open drain · bf814720
      Rabeeh Khoury authored
      
      
      This patch is important for the MicroSOM implementation due to the
      following details -
      
      1. VIH of the Atheros phy is 1.7V.
      2. NVCC_ENET which is the power domain of the MDIO pad is driven by the
         PHY's LDO (i.e. either 1.8v or 2.5v).
      3. The MicroSOM implements an onbouard 1.6kohm pull up to 3.3v (R3000).
      
      In the case the PHY's LDO was 1.8v then there would be only a 100mV
      margin for the signal to be acknowledged as high (1.8v-1.7v).
      Due to that setting the pad as an open drain will let the 1.6kohm pull
      that signal high to 3.3 that assures enough margins to the PHY to be
      acked as '1' logic.
      
      Signed-off-by: default avatarRabeeh Khoury <rabeeh@solid-run.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
      bf814720
    • Tero Kristo's avatar
      ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates · 8fd46439
      Tero Kristo authored
      
      
      Similarly to DRA7, OMAP5 has l3 and l4 clock rates incorrectly calculated.
      Fixed by using proper divider clock types for the clock nodes.
      
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      Reported-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Tested-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      8fd46439
  7. Aug 26, 2014
  8. Aug 25, 2014