- Jun 21, 2017
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David S. Miller authored
John Crispin says: ==================== net-next: mediatek: various performance improvements During development we mainly ran testing using iperf doing 1500 byte tcp frames. It was pointed out recently, that the driver does not perform very well when using 512 byte udp frames. The biggest problem was that RPS was not working as no rx queue was being set. fixing this more than doubled the throughput. Additionally the IRQ mask register is now locked independently for RX and TX. RX IRQ aggregation is also added. With all these patches applied we can almost triple the throughput. While at it we also add PHY status change reporting for GMACs connecting directly to a PHY. ==================== Signed-off-by:
David S. Miller <davem@davemloft.net>
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John Crispin authored
The get_rps_cpu() function will not do any RPS on the data flow when no queue is setup and always use the current cpu where the IRQ was handled to also handle the backlog. As we only have one physical queue we always set this to 0 unconditionally. Signed-off-by:
John Crispin <john@phrozen.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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John Crispin authored
Originally the driver only utilised the new QDMA engine. The current code still assumes this is the case when locking the IRQ mask register. Since RX now runs on the old style PDMA engine we can add a second lock. This patch reduces the IRQ latency as the TX and RX path no longer need to wait on each other under heavy load. Signed-off-by:
John Crispin <john@phrozen.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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John Crispin authored
The PDMA engine used for RX allows IRQ aggregation. The patch sets up the corresponding registers to aggregate 4 IRQs into one. Using aggregation reduces the load on the core handling to a quarter thus reducing IRQ latency and increasing RX performance by around 10%. Signed-off-by:
John Crispin <john@phrozen.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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John Crispin authored
Currently PHY status changes are only printed for DSA ports. This patch adds code to also print status changes for non-fixed links. Signed-off-by:
John Crispin <john@phrozen.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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David S. Miller authored
Matthias Schiffer says: ==================== vxlan: cleanup and IPv6 link-local support Running VXLANs over IPv6 link-local addresses allows to use them as a drop-in replacement for VLANs, avoiding to allocate additional outer IP addresses to run the VXLAN over. Since v1, I have added a lot more consistency checks to the address configuration, making sure address families and scopes match. To simplify the implementation, I also did some general refactoring of the configuration handling in the new first patch of the series. The second patch is more cleanup; is slightly touches OVS code, so that list is in CC this time, too. As in v1, the last two patches actually make VXLAN over IPv6 link-local work, and allow multiple VXLANs with the same VNI and port, as long as link-local addresses on different interfaces are used. As suggested, I now store in the flags field if the VXLAN uses link-local addresses or not. v3 removes log messages as suggested by Roopa Prabhu (as it is very unusual for errors in netlink requests to be printed to the kernel log.) The commit message of patch 5 has been extended to add a note about IPv4. ==================== Signed-off-by:
David S. Miller <davem@davemloft.net>
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Matthias Schiffer authored
As link-local addresses are only valid for a single interface, we can allow to use the same VNI for multiple independent VXLANs, as long as the used interfaces are distinct. This way, VXLANs can always be used as a drop-in replacement for VLANs with greater ID space. This also extends VNI lookup to respect the ifindex when link-local IPv6 addresses are used, so using the same VNI on multiple interfaces can actually work. Signed-off-by:
Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Matthias Schiffer authored
If VXLAN is run over link-local IPv6 addresses, it is necessary to store the ifindex in the FDB entries. Otherwise, the used interface is undefined and unicast communication will most likely fail. Support for link-local IPv4 addresses should be possible as well, but as the semantics aren't as well defined as for IPv6, and there doesn't seem to be much interest in having the support, it's not implemented for now. Signed-off-by:
Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Matthias Schiffer authored
* Multicast addresses are never valid as local address * Link-local IPv6 unicast addresses may only be used as remote when the local address is link-local as well * Don't allow link-local IPv6 local/remote addresses without interface We also store in the flags field if link-local addresses are used for the follow-up patches that actually make VXLAN over link-local IPv6 work. Signed-off-by:
Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Matthias Schiffer authored
Address families of source and destination addresses must match, and changelink operations can't change the address family. In addition, always use the VXLAN_F_IPV6 to check if a VXLAN device uses IPv4 or IPv6. Signed-off-by:
Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Matthias Schiffer authored
There is no good reason to keep the flags twice in vxlan_dev and vxlan_config. Signed-off-by:
Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Matthias Schiffer authored
The vxlan_dev_configure function was mixing validation and application of the vxlan configuration; this could easily lead to bugs with the changelink operation, as it was hard to see if the function wcould return an error after parts of the configuration had already been applied. This commit splits validation and application out of vxlan_dev_configure as separate functions to make it clearer where error returns are allowed and where the vxlan_dev or net_device may be configured. Log messages in these functions are removed, as it is generally unexpected to find error output for netlink requests in the kernel log. Userspace should be able to handle errors based on the error codes returned via netlink just fine. In addition, some validation and initialization is moved to vxlan_validate and vxlan_setup respectively to improve grouping of similar settings. Finally, this also fixes two actual bugs: * if set, conf->mtu would overwrite dev->mtu in each changelink operation, reverting other changes of dev->mtu * the "if (!conf->dst_port)" branch would never be run, as conf->dst_port was set in vxlan_setup before. This caused VXLAN-GPE to use the same default port as other VXLAN sockets instead of the intended IANA-assigned 4790. Signed-off-by:
Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by:
David S. Miller <davem@davemloft.net>
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David S. Miller authored
yuan linyu says: ==================== net: more skb_put_[data:zero] related work yuan linyu (3): net: introduce __skb_put_[zero, data, u8] net: replace more place to skb_put_[data:zero] net: manual clean code which call skb_put_[data:zero] ==================== Signed-off-by:
David S. Miller <davem@davemloft.net>
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yuan linyu authored
Signed-off-by:
yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Signed-off-by:
David S. Miller <davem@davemloft.net>
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yuan linyu authored
spatch file, @@ expression skb, len, data; type t; @@ -memcpy((t *)skb_put(skb, len), data, len); +skb_put_data(skb, data, len); @@ identifier p; expression skb, len, data; type t; @@ -p = (t *)memset(skb_put(skb, len), data, len); +p = skb_put_zero(skb, len); @@ expression skb, len, data; type t; @@ -memcpy((t *)__skb_put(skb, len), data, len); +__skb_put_data(skb, data, len); @@ identifier p; expression skb, len, data; type t; @@ -p = (t *)memset(__skb_put(skb, len), data, len); +p = __skb_put_zero(skb, len); Signed-off-by:
yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Signed-off-by:
David S. Miller <davem@davemloft.net>
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yuan linyu authored
follow Johannes Berg, semantic patch file as below, @@ identifier p, p2; expression len; expression skb; type t, t2; @@ ( -p = __skb_put(skb, len); +p = __skb_put_zero(skb, len); | -p = (t)__skb_put(skb, len); +p = __skb_put_zero(skb, len); ) ... when != p ( p2 = (t2)p; -memset(p2, 0, len); | -memset(p, 0, len); ) @@ identifier p; expression len; expression skb; type t; @@ ( -t p = __skb_put(skb, len); +t p = __skb_put_zero(skb, len); ) ... when != p ( -memset(p, 0, len); ) @@ type t, t2; identifier p, p2; expression skb; @@ t *p; ... ( -p = __skb_put(skb, sizeof(t)); +p = __skb_put_zero(skb, sizeof(t)); | -p = (t *)__skb_put(skb, sizeof(t)); +p = __skb_put_zero(skb, sizeof(t)); ) ... when != p ( p2 = (t2)p; -memset(p2, 0, sizeof(*p)); | -memset(p, 0, sizeof(*p)); ) @@ expression skb, len; @@ -memset(__skb_put(skb, len), 0, len); +__skb_put_zero(skb, len); @@ expression skb, len, data; @@ -memcpy(__skb_put(skb, len), data, len); +__skb_put_data(skb, data, len); @@ expression SKB, C, S; typedef u8; identifier fn = {__skb_put}; fresh identifier fn2 = fn ## "_u8"; @@ - *(u8 *)fn(SKB, S) = C; + fn2(SKB, C); Signed-off-by:
yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Kill the remaining shift macro in favor of calculating at compile time its value from the more descriptive mask, which gives us a better representation of the register layout. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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David S. Miller authored
Vivien Didelot says: ==================== net: dsa: Global 2 cosmetics Similarly to what has been done for the Port and Global 1 registers, this patch series prefixes and documents the macros of Global 2. It brings no functional changes except for 1/10 which fixes the IRL init for 88E6390 family. Changes in v2: make *_g2_irl_init_all static inline without NET_DSA_MV88E6XXX_GLOBAL2 and compile test with and without the symbol. ==================== Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Prefix and document the remaining Global 2 registers macros. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
The Marvell 88E6352 family has a Global 2 register dedicated to the watchdog setup. But the 88E6390 turned it into an indirect table. Prefix and document that. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Prefix and document the Global 2 Switch MAC registers macros. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Prefix and document the Global 2 EEPROM registers macros. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Prefix and document the Global 2 Cross-chip Port VLAN registers macros. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Prefix and document the Global 2 MGMT registers macros. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Prefix and document the Global 2 Device Mapping macros. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Prefix and document the Global 2 Trunk registers macros. At the same time, fix the hask -> hash typo and use the mv88e6xxx_port_mask helper. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Marvell chips with an SMI PHY access in Global 2 registers handle both Clause 22 and Clause 45 of IEEE 802.3. The 88E6390 family has addition bits to target the internal or external PHYs connected to the device, and a Setup function in addition to the default (register) Access function. Prefix the SMI PHY Command and Data registers macros, implement clear helpers for Clause 22 and 44 Access functions, rename variable to match the SMI and switch vocabulary (device and register addresses for Clause 22 and port and device class for Clause 45.) Finally do not use complex macros but simple 16-bit mask to document the registers organization. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vivien Didelot authored
Some Marvell chips have an Ingress Rate Limit unit. But the command values slightly differs between models: 88E6352 use 3-bit for operations while 88E6390 use different 2-bit operations. This commit kills the IRL flags in favor of a new operation implementing the "Init all resources to the initial state" operation. This fixes the operation of 88E6390 family where 0x1000 means Read the selected resource 0, register 0 on port 16, instead of init all. A mv88e6xxx_irl_setup helper is added to wrap the operation call. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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David S. Miller authored
Icenowy Zheng says: ==================== net-next: stmmac: dwmac-sun8i: add support for V3s Allwinner V3s features an EMAC like the on in H3, but without external MII interfaces, so being not able really to use RMII/RGMII. And it has a different default value of syscon (0x38000 instead of 0x58000 on H3), which shows a problem that the EMAC clock freq should be 24MHz. (Both H3 and V3s SoCs doesn't have extra xtal input for EPHY, and the main xtal is 24MHz. The default value of H3 is set to 24MHz, but the V3s default value is set to 25MHz). First two patches are device tree binding patches, the third forces the frequency to 24MHz and the fourth really add the V3s support. ==================== Signed-off-by:
David S. Miller <davem@davemloft.net>
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Icenowy Zheng authored
Allwinner V3s SoC has an Ethernet MAC and an internal PHY like the ones in H3 SoC, however the MAC has no external *MII interfaces available at GPIOs, thus only MII connection to internal PHY is supported. Add this variant of EMAC to dwmac-sun8i driver. The default value of the syscon EMAC-related register seems to have changed from H3, but it seems to be a harmless change. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Icenowy Zheng authored
The EPHY control part of the EMAC syscon register has a bit called CLK_SEL. On the datasheet it says that if it's 0 the EPHY clock is 25MHz and if it's 1 the clock is 24MHz. However, according to the datasheets, no Allwinner SoC with EPHY has any extra xtal input pins for the EPHY, and the system xtal is 24MHz. That means the EPHY is not possible to get a 25MHz xtal input, and thus the frequency can only be 24MHz. It doesn't matter on H3 as the default value of H3 is 24MHz, however on V3s the default value is wrongly set to 25MHz, which prevented the EPHY from working properly. Force the EPHY clock frequency to 24MHz. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Icenowy Zheng authored
Allwinner V3s SoC has a syscon like the one in H3. Add its compatible string. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Icenowy Zheng authored
Allwinner V3s SoC has a Ethernet MAC like the one in Allwinner H3, but have no external MII capability. That means that it can only use the EPHY and cannot do Gbps transmission. Add binding for it. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
David S. Miller <davem@davemloft.net>
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David S. Miller authored
Lucas Bates says: ==================== net: Introduction of the tc tests Apologies for sending this as one big patch. I've been sitting on this a little too long, but it's ready and I wanted to get it out. There are a limited number of tests to start - I plan to add more on a regular basis. ==================== Signed-off-by:
David S. Miller <davem@davemloft.net>
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Lucas Bates authored
Add the beginnings of a testsuite for tc functionality in the kernel. These are a series of unit tests that use the tc executable and verify the success of those commands by checking both the exit codes and the output from tc's 'show' operation. To run the tests: # cd tools/testing/selftests/tc-testing # sudo ./tdc.py You can specify the tc executable to use with the -p argument on the command line or editing the 'TC' variable in tdc_config.py. Refer to the README for full details on how to run. The initial complement of test cases are limited mostly to tc actions. Test cases are most welcome; see the creating-testcases subdirectory for help in creating them. Signed-off-by:
Lucas Bates <lucasb@mojatatu.com> Signed-off-by:
Jamal Hadi Salim <jhs@mojatatu.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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David S. Miller authored
Yuval Mintz says: ==================== qed*: RDMA and infrastructure for iWARP This series focuses on RDMA in general with emphasis on required changes toward adding iWARP support. The vast majority of the changes introduced are in qed/qede, with a couple of small changes to qedr [mentioned below]. The infrastructure changes: - Patch #1 adds the ability to pass PBL memory externally for a newly created chain. - Patches #4, #5 rename qede_roce.[ch] into qede_rdma.[ch] + change prefixes from _roce_ to _rdma_, as the API between qede and qedr is agnostic to the variant of the RDMA protocol used. These patches also touch qedr [basically to align it with the renaming, nothing more]. - Patch #7 replaces the current SPQ async mechanism into serving registered callbacks [before adding iWARP which would add another client in need of this sort of functionallity]. The non-infrastrucutre changes: - Patches #2, #3 contain DCB-related changes to better align RDMA with configured DCB. - Patch #6 contains a minor [mostly theoretical fix] to release flow. Changes from previous versions ------------------------------ - V4: This is actually a repost of V3 due to some confusion regarding the sent cover-letter - V3: Add commit log message in #4 indicating change in header inclusion - V2: Add several inclusion into qede_rdma.h to have proper declarations of all variable types used in it ==================== Signed-off-by:
David S. Miller <davem@davemloft.net>
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Michal Kalderon authored
Whenever firmware indicates that there's an async indication it needs to handle, there's a switch-case where the right functionality is called based on function's personality and information. Before iWARP is added [as yet another client], switch over the SPQ into a callback-registered mechanism, allowing registration of the relevant event-processing logic based on the function's personality. This allows us to tidy the code by removing protocol-specifics from a common file. Signed-off-by:
Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by:
Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Michal Kalderon authored
Driver needs to wait for all resources to return from FW before it can send the FUNC_CLOSE ramrod. Signed-off-by:
Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by:
Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Michal Kalderon authored
Rename the functions common to both iWARP and RoCE to have a prefix of _rdma_ instead of _roce_. Signed-off-by:
Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by:
Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Michal Kalderon authored
Once we have iWARP support, the qede portion of the qedr<->qede would serve all the RDMA protocols - so rename the file to be appropriate to its function. While we're at it, we're also moving a couple of inclusions to it into .h files and adding includes to make sure it contains all type definitions it requires. Signed-off-by:
Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by:
Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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