- Jul 19, 2014
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Mateusz Krawczuk authored
Add DTS for s5pc110 boards: goni, aquila, smdkc110 s5pv210: smdkv210, tiny210, torbreck Signed-off-by:
Mateusz Krawczuk <m.krawczuk@partner.samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> [t.figa: Rebased, fixed merge conflicts, neatened.] Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Mateusz Krawczuk authored
Add generic device tree for s5pv210 and s5pv210-pinctrl Signed-off-by:
Mateusz Krawczuk <m.krawczuk@partner.samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Mateusz Krawczuk authored
This patch adds board file that will be used to boot S5PV210/S5PC110-based boards using Device Tree. Signed-off-by:
Mateusz Krawczuk <m.krawczuk@partner.samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> [t.figa: Rebased and cleaned-up a bit.] Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Tomasz Figa authored
Since S5PV210 now has a complete clock driver using Common Clock Framework, there is no reason to keep the old code. Remove it together with the whole legacy Samsung-specific clock framework which no longer has any users. Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Mateusz Krawczuk authored
This patch migrates the s5pv210 platform to use new clock driver using Common Clock Framework. Signed-off-by:
Mateusz Krawczuk <m.krawczuk@partner.samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> [t.figa: Rebased and fixed merge conflicts.] Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- Jul 15, 2014
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Pankaj Dubey authored
Add support for mapping Samsung Power Management Unit (PMU) base address from device tree. Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Pankaj Dubey authored
This patch removes unnecessary header file inclusion from pmu.c. Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Pankaj Dubey authored
Current "pm_domain.c" file uses "S5P_INT_LOCAL_PWR_EN" definition from "regs-pmu.h" and hence needs to include this header file. As there is no other user of "S5P_INT_LOCAL_PWR_EN" definition other than pm_domain, to remove "regs-pmu.h" header file dependency from "pm_domain.c" it's better we define this definition in "pm_domain.c" file itself and thus it will help in removing header file inclusion from "pm_domain.c". Also removing "S5P_" prefix from macro. Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Pankaj Dubey authored
Many files under "arm/mach-exynos" are having file path in file comment section which is invalid now. So for better code maintainability let's remove them. Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Pankaj Dubey authored
While making PMU implementation to be device tree based, there are few register offsets related with SYSREG present in regs-pmu.h, so let's make a new header file "regs-sys.h" to keep all such SYSREG related register offsets and remove them from "regs-pmu.h" Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Pankaj Dubey authored
As machine function ops are used only in this file let's make them static. Also remove unused and unwanted declarations from common.h. Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Sachin Kamat authored
PINCTRL_EXYNOS is always selected by Exynos platform in its machine Kconfig. Thus the code in the else part is never used. Remove it. Signed-off-by:
Sachin Kamat <sachin.kamat@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Sachin Kamat authored
In a multiplatform config, the low level debug option shows several UART port entries. Improve the user visible string so that it becomes clear to the user about Samsung UART ports. While at it also remove some lines from the help text that are no longer applicable across all Samsung platforms. Signed-off-by:
Sachin Kamat <sachin.kamat@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- Jul 13, 2014
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Kukjin Kim authored
This patch removes supporting codes for s5pc100 because no more used now. [jason@lakedaemon.net: for drivers/irqchip/Kconfig] Acked-by:
Jason Cooper <jason@lakedaemon.net> Acked-by:
Arnd Bergmann <arnd@arndb.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Bo Shen authored
Add clocks for usb device, or else switch to CCF, the gadget won't work. Reported-by:
Jiri Prchal <jiri.prchal@aksignal.cz> Signed-off-by:
Bo Shen <voice.shen@atmel.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Tested-by:
Jiri Prchal <jiri.prchal@aksignal.cz> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- Jul 11, 2014
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Tomasz Figa authored
Currently, the exynos cpuidle driver works correctly only on exynos4210 and 5250. Trying to use it with just one CPU online on any other exynos SoCs will lead to system failure, due to unsupported AFTR mode on other SoCs. This patch fixes the problem by registering the driver only on supported SoCs and letting others simply use default WFI mode until support for them is added. Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Arun Kumar K authored
Adding the optional clock property for the mfc_pd for handling the re-parenting while pd on/off. Signed-off-by:
Arun Kumar K <arun.kk@samsung.com> Signed-off-by:
Shaik Ameer Basha <shaik.ameer@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Prathyush K authored
While powering on/off a local powerdomain in exynos5 chipsets, the input clocks to each device gets modified. This behaviour is based on the SYSCLK_SYS_PWR_REG registers. E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC (aclk333) gets modified to oscclk = 0x1, no change in clocks. The recommended value of SYSCLK_SYS_PWR_REG before power gating any domain is 0x0. So we must also restore the clocks while powering on a domain everytime. This patch adds the framework for getting the required mux and parent clocks through a power domain device node. With this patch, while powering off a domain, parent is set to oscclk and while powering back on, its re-set to the correct parent which is as per the recommended pd on/off sequence. Signed-off-by:
Prathyush K <prathyush.k@samsung.com> Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
Arun Kumar K <arun.kk@samsung.com> Signed-off-by:
Shaik Ameer Basha <shaik.ameer@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- Jul 08, 2014
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Jyri Sarha authored
This code is not working currently and it can be removed. There is a conflict in sharing resources with the actual HDMI driver and with the ASoC HDMI audio DAI driver. Signed-off-by:
Jyri Sarha <jsarha@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Shawn Guo authored
Let's say clock A and B are two gate clocks that share the same register bit in hardware. Therefore they are registered as shared gate clocks with imx_clk_gate2_shared(). In a scenario that only clock A is enabled by clk_enable(A) while B is not used, the shared gate will be unexpectedly disabled in hardware. It happens because clk_enable(A) increments the share_count from 0 to 1, while clock B is unused to clock core, and therefore the core function will just disable B by calling clk->ops->disable() directly. The consequence of that call is share_count is decremented to 0 and the gate is disabled in hardware, even though clock A is still in use. The patch fixes the issue by initializing the share_count per hardware state and returns enable state per share_count from .is_enabled() hook, in case it's a shared gate. While at it, add a check in clk_gate2_disable() to ensure it's never called with a zero share_count. Reported-by:
Fabio Estevam <fabio.estevam@freescale.com> Fixes: f9f28cdf ("ARM: imx: add shared gate clock support") Signed-off-by:
Shawn Guo <shawn.guo@freescale.com> Tested-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Tushar Behera authored
Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux. As per the user manual, it should be CLK_MAU_EPLL. The problem surfaced when the bootloader in Peach-pit board set the EPLL clock as the parent of AUDSS mux. While booting the kernel, we used to get a system hang during late boot if CLK_MAU_EPLL was disabled. Signed-off-by:
Tushar Behera <tushar.b@samsung.com> Signed-off-by:
Shaik Ameer Basha <shaik.ameer@samsung.com> Reported-by:
Kevin Hilman <khilman@linaro.org> Tested-by:
Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Sachin Kamat authored
Almost all Exynos-series of SoCs that run in secure mode don't need additional offset for every CPU, with Exynos4412 being the only exception. Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420). While at it, fix the coding style (space around *). Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by:
Tushar Behera <tushar.behera@linaro.org> Tested-by:
Andreas Faerber <afaerber@suse.de> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Kukjin Kim authored
This patch removes supporting codes for s5p6440 and s5p6450 because seems no more used now. And if its supporting is required, DT based codes should be supprted next time. Acked-by:
Arnd Bergmann <arnd@arndb.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Russell King authored
The revision checking in l2c310_enable() was not correct; we were masking the part number rather than the revision number. Fix this to use the correct macro. Fixes: 4374d649 ("ARM: l2c: add automatic enable of early BRESP") Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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- Jul 07, 2014
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Enric Balletbo i Serra authored
As this board use external clock for RMII interface we should specify 'rmii' phy mode and 'rmii-clock-ext' to make ethernet working. Signed-off-by:
Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Peter Ujfalusi authored
The use of FIFO in McASP can reduce the risk of audio under/overrun and lowers the load on the memories since the DMA will operate in bursts. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Peter Ujfalusi authored
The use of FIFO in McASP can reduce the risk of audio under/overrun and lowers the load on the memories since the DMA will operate in bursts. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Guido Martínez authored
Currently, child nodes of the gpmc node are iterated and probed regardless of their 'status' property. This means adding 'status = "disabled";' has no effect. This patch changes the iteration to only probe nodes marked as available. Signed-off-by:
Guido Martínez <guido@vanguardiasur.com.ar> Tested-by:
Pekon Gupta <pekon@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Suman Anna authored
The DSP platform device for TI DSP/Bridge is currently created unconditionally whenever CONFIG_TIDSPBRIDGE is enabled. This device should only be created on OMAP34xx/ OMAP36xx SoCs, and not for other OMAP3 derived SoCs or when booting multi-arch images on other SoCs. So, add a check for the SoC family both before creating the device and allocating the carveout memory for the device. Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
After clarification from the hardware team it was found that this 1.8V PHY supply can't be switched OFF when SoC is Active. Since the PHY IPs don't contain isolation logic built in the design to allow the power rail to be switched off, there is a very high risk of IP reliability and additional leakage paths which can result in additional power consumption. The only scenario where this rail can be switched off is part of Power on reset sequencing, but it needs to be kept always-on during operation. This patch is required for proper functionality of USB, SATA and PCIe on DRA7-evm. CC: Rajendra Nayak <rnayak@ti.com> CC: Tero Kristo <t-kristo@ti.com> Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Nishanth Menon authored
omap44xx_restart is defined as a static void inline when DRA7/AM437X is defined alone, which implies that the restart function is no longer functional even though it is built in. So, fix the definition of the same. Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tero Kristo authored
The divider value provided to the _dpll_test_fint can reach value of 256 with J type DPLLs (USB etc.), which causes an overflow with the u8 datatype. Fix this by changing the parameter to be an int instead. Signed-off-by:
Tero Kristo <t-kristo@ti.com> [paul@pwsan.com: changed type of 'n' to unsigned int] Signed-off-by:
Paul Walmsley <paul@pwsan.com>
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Roger Quadros authored
Add the sysconfig class bits for the Super Speed USB controllers Signed-off-by:
Roger Quadros <rogerq@ti.com> Reviewed-by:
Rajendra Nayak <rnayak@ti.com> Tested-by:
Sekhar Nori <nsekhar@ti.com> Signed-off-by:
Paul Walmsley <paul@pwsan.com>
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Roger Quadros authored
Get rid of optional clock as that is now managed by the AHCI platform driver. Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..) is passed as the second memory resource in the device tree. Signed-off-by:
Roger Quadros <rogerq@ti.com> Reviewed-by:
Rajendra Nayak <rnayak@ti.com> Tested-by:
Sekhar Nori <nsekhar@ti.com> Signed-off-by:
Paul Walmsley <paul@pwsan.com>
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Suman Anna authored
The commit 7be914f2 {ARM: OMAP3: PRM/CM: Cleanup unused header} removed some of the macros used by the TI DSP/Bridge driver. This fixes the following build errors when trying to build DSP/Bridge driver (disabled at present), otherwise results in the following build errors: drivers/staging/tidspbridge/core/tiomap3430.c:531:31: error: 'OMAP3430_AUTO_IVA2_DPLL_SHIFT' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430.c:531:31: note: each undeclared identifier is reported only once for each function it appears in make[3]: *** [drivers/staging/tidspbridge/core/tiomap3430.o] Error 1 make[3]: *** Waiting for unfinished jobs.... drivers/staging/tidspbridge/core/tiomap_io.c: In function 'sm_interrupt_dsp': drivers/staging/tidspbridge/core/tiomap_io.c:404:31: error: 'OMAP3430_AUTO_IVA2_DPLL_SHIFT' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap_io.c:404:31: note: each undeclared identifier is reported only once for each function it appears in drivers/staging/tidspbridge/core/tiomap_io.c:414:12: error: 'OMAP3430_IVA2_DPLL_FREQSEL_SHIFT' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap_io.c:415:12: error: 'OMAP3430_EN_IVA2_DPLL_SHIFT' undeclared (first use in this function) make[3]: *** [drivers/staging/tidspbridge/core/tiomap_io.o] Error 1 drivers/staging/tidspbridge/core/tiomap3430_pwr.c: In function 'dsp_clk_wakeup_event_ctrl': drivers/staging/tidspbridge/core/tiomap3430_pwr.c:442:19: error: 'OMAP3430_GRPSEL_GPT5_MASK' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430_pwr.c:442:19: note: each undeclared identifier is reported only once for each function it appears in drivers/staging/tidspbridge/core/tiomap3430_pwr.c:455:19: error: 'OMAP3430_GRPSEL_GPT6_MASK' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430_pwr.c:468:19: error: 'OMAP3430_GRPSEL_GPT7_MASK' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430_pwr.c:481:19: error: 'OMAP3430_GRPSEL_GPT8_MASK' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430_pwr.c:494:19: error: 'OMAP3430_GRPSEL_MCBSP1_MASK' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430_pwr.c:546:19: error: 'OMAP3430_GRPSEL_MCBSP5_MASK' undeclared (first use in this function) make[3]: *** [drivers/staging/tidspbridge/core/tiomap3430_pwr.o] Error 1 make[2]: *** [drivers/staging/tidspbridge] Error 2 Fixes: 7be914f2 (ARM: OMAP3: PRM/CM: Cleanup unused header) Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Paul Walmsley <paul@pwsan.com>
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- Jul 05, 2014
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Maxime Ripard authored
This partly reverts commits 55360050 (ARM: sunxi: Remove reset code from the platform) and 5e669ec5 (ARM: sunxi: Remove init_machine callback) for the sun4i, sun5i and sun7i families. This is needed because the watchdog counterpart of these commits was dropped, and didn't make it into 3.16. In order to still be able to reboot the board, we need to reintroduce that code. Of course, the long term view is still to get rid of that code in mach-sunxi. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Jaewon Kim authored
pwm-cells should be 3. Third cell is optional PWM flags. And This flag supported by this binding is PWM_POLARITY_INVERTED. Signed-off-by:
Jaewon Kim <jaewon02.kim@samsung.com> Reviewed-by:
Sachin Kamat <sachin.kamat@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Abhilash Kesavan authored
Commit 1754c42e ("ARM: exynos: move sysram info to exynos.c") missed out the CONFIG_ prefix causing exynos_sysram_init() to get called twice for SMP configurations. Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by:
Sachin Kamat <sachin.kamat@samsug.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- Jul 04, 2014
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Rajendra Nayak authored
Without the patch: /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate 532000000 /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate 532000000 /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate 532000000 With the patch: /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate 532000000 /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate 266000000 /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate 133000000 The l3 clock derived from core DPLL is actually a divider clock, with the default divider set to 2. l4 then derived from l3 is a fixed factor clock, but the fixed divider is 2 and not 1. Which means the l3 clock is half of core DPLLs h12x2 and l4 is half of l3 (as seen with this patch) Signed-off-by:
Rajendra Nayak <rnayak@ti.com> Signed-off-by:
Tero Kristo <t-kristo@ti.com>
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- Jul 02, 2014
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Jon Medhurst authored
Conditionally compile kprobes test cases for ARMv5 instructions to avoid compilation errors with ARMv4 targets like: /tmp/cc7Tx8ST.s:16740: Error: selected processor does not support ARM mode `clz r0,r0' Signed-off-by:
Jon Medhurst <tixy@linaro.org>
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