- Jul 26, 2014
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Doug Anderson authored
This allows the "make dtbs" target to work. Signed-off-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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Heiko Stuebner authored
There exist 2 variants using either the act8846 or rk808 as pmic, while the rest of the board stays the same. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Will Deacon <will.deacon@arm.com> Reviewed-by:
Doug Anderson <dianders@chromium.org> Tested-by:
Doug Anderson <dianders@chromium.org> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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Heiko Stuebner authored
Node definitions shared by all rk3288 based boards. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Will Deacon <will.deacon@arm.com> Tested-by:
Doug Anderson <dianders@chromium.org> Reviewed-by:
Doug Anderson <dianders@chromium.org> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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Heiko Stuebner authored
Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Will Deacon <will.deacon@arm.com> Reviewed-by:
Doug Anderson <dianders@chromium.org> Tested-by:
Doug Anderson <dianders@chromium.org> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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Heiko Stuebner authored
The new rk3288 needs a bigger gpio space, as it has 9 gpio banks. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
Doug Anderson <dianders@chromium.org> Tested-by:
Doug Anderson <dianders@chromium.org> Tested-by:
Will Deacon <will.deacon@arm.com> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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Heiko Stuebner authored
The uarts on rk3288 are still compatible with the dw_8250, but located at a different position and need DEBUG_UART_8250_WORD enabled. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
Doug Anderson <dianders@chromium.org> Tested-by:
Doug Anderson <dianders@chromium.org> Tested-by:
Will Deacon <will.deacon@arm.com> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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Heiko Stuebner authored
The debug uart settings from the DEBUG_RK3X_UART options are usable on all Rockchip SoCs from the rk30xx and rk31xx series but not on the new rk3288 SoCs. Thus clarify their use to prevent confusion. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
Doug Anderson <dianders@chromium.org> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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- Jul 14, 2014
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Heiko Stübner authored
All known Rockchip SoCs have a reset controller in their CRUs, so it's helpful to have the reset controller framework selected by default, only be deselected by the user in special cases. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Acked-By:
Max Schwarz <max.schwarz@online.de> Tested-By:
Max Schwarz <max.schwarz@online.de> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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- Jun 29, 2014
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Will Deacon authored
On the syscall tracing path, we call out to secure_computing() to allow seccomp to check the syscall number being attempted. As part of this, a SIGTRAP may be sent to the tracer and the syscall could be re-written by a subsequent SET_SYSCALL ptrace request. Unfortunately, this new syscall is ignored by the current code unless TIF_SYSCALL_TRACE is also set on the current thread. This patch slightly reworks the enter path of the syscall tracing code so that we always reload the syscall number from current_thread_info()->syscall after the potential ptrace traps. Acked-by:
Kees Cook <keescook@chromium.org> Tested-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Laura Abbott authored
Commit 1c2f87c2 (ARM: 8025/1: Get rid of meminfo) changed find_limits to use memblock_get_current_limit for calculating the max_low pfn. nommu targets never actually set a limit on memblock though which means memblock_get_current_limit will just return the default value. Set the memblock_limit to be the end of DDR to make sure bounds are calculated correctly. Signed-off-by:
Laura Abbott <lauraa@codeaurora.org> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Andrea Adami authored
The CFI mapping is now perfect so we can expose the top block, read only. There isn't much to read, though, just the sharpsl_params values. Signed-off-by:
Andrea Adami <andrea.adami@gmail.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Andrea Adami authored
Reverts commit d26b17ed ARM: sa1100: collie.c: fall back to jedec_probe flash detection Unfortunately the detection was challenged on the defective unit used for tests: one of the NOR chips did not respond to the CFI query. Moreover that bad device needed extra delays on erase-suspend/resume cycles. Tested personally on 3 different units and with feedback of two other users. Signed-off-by:
Andrea Adami <andrea.adami@gmail.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Nicolas Pitre authored
The sync_phys variable has been replaced by link time computation in mcpm_head.S before the code was submitted upstream. Signed-off-by:
Nicolas Pitre <nico@linaro.org> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Thomas Petazzoni authored
When a PL310 cache is used on a system that provides hardware coherency, the outer cache sync operation is useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe controller and the Cortex-A9. To avoid this, this commit introduces a new Device Tree property 'arm,io-coherent' for the L2 cache controller node, valid only for the PL310 cache. It identifies the usage of the PL310 cache in an I/O coherent configuration. Internally, it makes the driver disable the outer cache sync operation. Note that technically speaking, a fully coherent system wouldn't require any of the other .outer_cache operations. However, in practice, when booting secondary CPUs, these are not yet coherent, and therefore a set of cache maintenance operations are necessary at this point. This explains why we keep the other .outer_cache operations and only ->sync is disabled. While in theory any write to a PL310 register could cause the deadlock, in practice, disabling ->sync is sufficient to workaround the deadlock, since the other cache maintenance operations are only used in very specific situations. Contrary to previous versions of this patch, this new version does not simply NULL-ify the ->sync member, because the l2c_init_data structures are now 'const' and therefore cannot be modified, which is a good thing. Therefore, this patch introduces a separate l2c_init_data instance, called of_l2c310_coherent_data. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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- Jun 26, 2014
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Alexandre Belloni authored
The at91sam9261 doesn't actually have a slow RC oscillator, remove it from the dtsi. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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- Jun 25, 2014
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Alexandre Belloni authored
Define at91sam9261ek's slow crystal frequencies. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Alexandre Belloni authored
mainck (CKGR_MCFR register) is actually using main_osc (CKGR_MOR register). Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Alexandre Belloni authored
ICPLL can only take 0 or 1, it got mixed with OUT which can be in the [0-3] range. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Alexandre Belloni authored
ICPLL can only take 0 or 1, it got mixed with OUT which can be in the [0-3] range. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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- Jun 24, 2014
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Linus Walleij authored
Commit 07e461cd "of: Ensure unique names without sacrificing determinism" caused a boot failure regression on the Integrator machines. The problem is probably caused by fiddling too much with the device tree population in the OF init function, such as passing the SoC bus device as parent when populating the device tree. This patch fixes the problem by: - Avoiding to explicitly look up the tree root - Look up devices needed before device population from the match only, passing NULL as root - Passing NULL as root and parent when calling of_platform_populate() After this the Integrators boot again. Tested on Integrator/AP and Integrator/CP. Cc: Grant Likely <grant.likely@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Gregory CLEMENT authored
Wildcards in compatible strings should be avoid. "marvell,armada38x" was recently introduced but was not yet used. The armada 385 SoC is a superset of the armada 380 SoC (with more CPUs and more PCIe slots). So this patch replaces the use of "marvell,armada38x" by the "marvell,armada380" string. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1403533011-21339-1-git-send-email-gregory.clement@free-electrons.com Acked-by:
Andrew Lunn <andrew@lunn.ch> Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
Commit eeb84545 ("ARM: dts: kirkwood: set Guruplug phy-connection-type to rgmii-id") added phy-connection-type properties to ethernet PHY nodes. Actually, the property has to be set for the ethernet port node instead. Fix it by moving the corresponding properties to the correct nodes. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1403555115-13111-1-git-send-email-sebastian.hesselbarth@gmail.com Fixes: eeb84545 : ('ARM: dts: kirkwood: set Guruplug phy-connection-type to rgmii-id') Cc: <stable@vger.kernel.org> # v3.16+ Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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- Jun 21, 2014
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Doug Anderson authored
On exynos mcpm systems the firmware is hardcoded to jump to an address in SRAM (0x02073000) when secondary CPUs come up. By default the firmware puts a bunch of code at that location. That code expects the kernel to fill in a few slots with addresses that it uses to jump back to the kernel's entry point for secondary CPUs. Originally (on prerelease hardware) this firmware code contained a bunch of workarounds to deal with boot ROM bugs. However on all shipped hardware we simply use this code to redirect to a kernel function for bringing up the CPUs. Let's stop relying on the code provided by the bootloader and just plumb in our own (simple) code jump to the kernel. This has the nice benefit of fixing problems due to the fact that older bootloaders (like the one shipped on the Samsung Chromebook 2) might have put slightly different code into this location. Once suspend/resume is implemented for systems using exynos-mcpm we'll need to make sure we reinstall our fixed up code after resume. ...but that's not anything new since IRAM (and thus the address of the mcpm_entry_point) is lost across suspend/resume anyway. Signed-off-by:
Doug Anderson <dianders@chromium.org> Acked-by:
Kevin Hilman <khilman@linaro.org> Tested-by:
Kevin Hilman <khilman@linaro.org> Acked-by:
Nicolas Pitre <nico@linaro.org> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Denis Carikli authored
The following commit: 89d7e5c1 mmc: sdhci-esdhc-imx: add runtime pm support has the effect of also disabling the hardware card detect in runtime pm. We switch to GPIO based detection to avoid this issue. This patch is based on: ARM: dts: imx51-babbage: Fix esdhc setup Signed-off-by:
Denis Carikli <denis@eukrea.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Sascha Hauer authored
Since commit 89d7e5c1 (mmc: sdhci-esdhc-imx: add runtime pm support), controller based card detection / write protection is not supported anymore by esdhc driver. Let's use GPIO for CD/WP on esdhc1 instead. While at it, fix cd gpio polarity for esdhc2. This is wrong and currently only works because the imx esdhc driver ignores the polarity. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Marek Vasut authored
Move the display {} node out of the soc {} node . This just aligns the DT with other boards, there is no functional change. Signed-off-by:
Marek Vasut <marex@denx.de> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Marek Vasut authored
The "port" node was misplaced in the original patch, therefore making the LCD dysfunctional on this board. Fix this by moving the "port" DT node into the "display {}" node. Signed-off-by:
Marek Vasut <marex@denx.de> Acked-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Thomas Petazzoni authored
On Marvell Armada platforms, the PMSU (Power Management Service Unit) controls a number of power management related activities, needed for things like suspend/resume, CPU hotplug, cpuidle or even simply SMP. Since cpuidle support was added for Armada XP, the pmsu.c file in arch/arm/mach-mvebu/ calls the cpu_suspend() and cpu_resume() ARM functions, which are only available when CONFIG_ARM_CPU_SUSPEND=y. Therefore, configurations that have CONFIG_ARM_CPU_SUSPEND disabled due to PM_SLEEP being disabled no longer build properly, due to undefined references to cpu_suspend() and cpu_resume(). To fix this, this patch simply ensures CONFIG_ARM_CPU_SUSPEND is always enabled for Marvell EBU v7 platforms. Doing things in a more fine-grained way would require a lot of #ifdef-ery in pmsu.c to isolate the parts that use cpu_suspend()/cpu_resume(), and those parts would anyway have been needed as soon as either one of suspend/resume, CPU hotplug or cpuidle was enabled. Reported-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1402488397-31381-1-git-send-email-thomas.petazzoni@free-electrons.com Acked-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Ezequiel Garcia authored
Currently the mvebu boards need to detect the SoC revision in order to apply some quirks needed to workaround issues found on I2C and thermal controllers present only in very early SoC. This detection requires PCI address translation to work, so we need to explicitly select OF_ADDRESS_PCI. This can be considered a partial revert of the following commit, that wrongly removed the option selection: commit 55400f3a Author: Rob Herring <robh@kernel.org> Date: Tue Apr 22 14:15:52 2014 -0500 ARM: mvebu: clean-up unneeded kconfig selects Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1402347165-19988-1-git-send-email-ezequiel.garcia@free-electrons.com Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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- Jun 20, 2014
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Fabio Estevam authored
Since commit 39b9004d (gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging) the ipuv3 core driver is no longer built bey default. Select CONFIG_IMX_IPUV3_CORE so that the core ipuv3 code can be built again. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Russell King authored
Commit ca8f0b0a ("ARM: ensure C page table setup code follows assembly code") did what it said on the tin, but some of the older CPU code omitted the default cache policy from their files. This results in the kernel running with the caches disabled. Fix this for ARM925. Reported-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Srinivas Kandagatla authored
This patch adds QCOM GSBI config option to multi_v7_defconfig. Serial driver on QCOM APQ8064 depends on GSBI driver, so without this patch there is no serial console on IF6410 board using multi_v7_defconfig. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- Jun 19, 2014
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Russell King authored
GCC 4.6.4 spits out the following warning when building perf_event_v7.c: arch/arm/kernel/perf_event_v7.c: In function 'krait_pmu_get_event_idx': arch/arm/kernel/perf_event_v7.c:1927:6: warning: 'bit' may be used uninitialized in this function While upgrading the version of gcc may solve this, the code can also be organised to be more efficient by not carrying more local variables than is necessary across the armv7pmu_get_event_idx function call. If we set 'bit' to -1 (which is invalid for clear_bit) we can use that as an indication whether we need to clear a bit after this function. Acked-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
A number of configurations spit out warnings similar to: warning: (SOC_IMX6 && SOC_VF610 && ARCH_OMAP4) selects PL310_ERRATA_588369 which has unmet direct dependencies (CACHE_L2X0) warning: (SOC_IMX6 && SOC_VF610 && ARCH_OMAP4) selects PL310_ERRATA_727915 which has unmet direct dependencies (CACHE_L2X0) Clean up the dependencies here: * PL310 symbols should only be selected when CACHE_L2X0 is enabled. * Since the cache-l2x0 code detects PL310 presence at runtime, and we will eventually get rid of CACHE_PL310, surround these errata options with an if CACHE_L2X0 conditional rather than repeating the dependency against each. Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Lee Jones authored
Two reasons for this rename. Firstly, it removes the camel case convention which isn't used by any other platform and secondly it matches the naming convention for the internal kernel, which can become annoying when flipping between the two. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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- Jun 18, 2014
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Ezequiel Garcia authored
Since commit: commit d93003e8 Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Date: Thu Apr 24 22:58:30 2014 +0100 ARM: 8042/1: iwmmxt: allow to build iWMMXt on Marvell PJ4B fixed the error that prevented Dove SoC from being built with the rest of the mvebu SoCs, we can now add it to the defconfig. In addition, this commit enables SERIAL_OF_PLATFORM, which is required to have UART on some of the boards. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Steven Rostedt authored
The clean up of CALLER_ADDR*() functions required the archs to either use the default __builtin_return_address(X) (where X > 0) or override it with something the arch can use. To override it, the arch would define ftrace_return_address(x). The arm architecture requires this to be redefined but instead of defining ftrace_return_address(x) it defined ftrace_return_addr(x). Fixes: eed542d6 (ftrace: Make CALLER_ADDRx macros more generic) Reported-by:
Geert Uytterhoeven <geert@linux-m68k.org> Tested-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
Steven Rostedt <rostedt@goodmis.org> Signed-off-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Abhilash Kesavan authored
We have an soc check to ensure that the scu and certain A9 specific registers are not accessed on Exynos5250 (which is A15 based). Rather than adding another soc specific check for 5420 let us test for the Cortex A9 primary part number. This resolves the below crash seen on exynos5420 during core switching after the CPUIdle consolidation series was merged. [ 155.975589] [<c0013174>] (scu_enable) from [<c001b0dc>] (exynos_cpu_pm_notifier+0x80/0xc4) [ 155.983833] [<c001b0dc>] (exynos_cpu_pm_notifier) from [<c003c1b0>] (notifier_call_chain+0x44/0x84) [ 155.992851] [<c003c1b0>] (notifier_call_chain) from [<c007a49c>] (cpu_pm_notify+0x20/0x3c) [ 156.001089] [<c007a49c>] (cpu_pm_notify) from [<c007a564>] (cpu_pm_exit+0x20/0x38) [ 156.008635] [<c007a564>] (cpu_pm_exit) from [<c0019e98>] (bL_switcher_thread+0x298/0x40c) [ 156.016788] [<c0019e98>] (bL_switcher_thread) from [<c003842c>] (kthread+0xcc/0xe8) [ 156.024426] [<c003842c>] (kthread) from [<c000e438>] (ret_from_fork+0x14/0x3c) [ 156.031621] Code: ea017fec c0530a00 c052e3f8 c0012dcc (e5903000 Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- Jun 17, 2014
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Rob Herring authored
The System Type menu is getting quite long with platforms and is inconsistent in handling of sub-arch specific options. Tidy up the menu by making platform options a menuconfig entry containing any platform specific config items. [arnd: change OMAP part according to suggestion from Tony Lindgren <tony@atomide.com>] Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Stephen Warren authored
Following 5d01b768 "mmc: simplify SDHCI Kconfig dependencies", SDHCI drivers that use MMC_SDHCI_PLTFM no longer select it, but instead depend on it. This means that multi_v7_defconfig no longer selects it, and hence many SDHCI drivers are no longer enabled. Explicitly enable MMC_SDHCI_PLTFM to solve this. Fixes: 5d01b768 ("mmc: simplify SDHCI Kconfig dependencies") Signed-off-by:
Stephen Warren <swarren@nvidia.com> Tested-by:
Matt Porter <mporter@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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