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    • Lionel Landwerlin's avatar
      drm/i915/perf: introduce global sseu pinning · 11ecbddd
      Lionel Landwerlin authored
      
      
      On Gen11 powergating half the execution units is a functional
      requirement when using the VME samplers. Not fullfilling this
      requirement can lead to hangs.
      
      This unfortunately plays fairly poorly with the NOA requirements. NOA
      requires a stable power configuration to maintain its configuration.
      
      As a result using OA (and NOA feeding into it) so far has required us
      to use a power configuration that can work for all contexts. The only
      power configuration fullfilling this is powergating half the execution
      units.
      
      This makes performance analysis for 3D workloads somewhat pointless.
      
      Failing to find a solution that would work for everybody, this change
      introduces a new i915-perf stream open parameter that punts the
      decision off to userspace. If this parameter is omitted, the existing
      Gen11 behavior remains (half EU array powergating).
      
      This change takes the initiative to move all perf related sseu
      configuration into i915_perf.c
      
      v2: Make parameter priviliged if different from default
      
      v3: Fix context modifying its sseu config while i915-perf is enabled
      
      v4: Always consider global sseu a privileged operation (Tvrtko)
          Override req_sseu point in intel_sseu_make_rpcs() (Tvrtko)
          Remove unrelated changes (Tvrtko)
      
      v5: Some typos (Tvrtko)
          Process sseu param in read_properties_unlocked() (Tvrtko)
      
      v6: Actually commit the bits from v5...
          Fixup some checkpath warnings
      
      v7: Only compare engine uabi field (Chris)
      
      Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200317132222.2638719-3-lionel.g.landwerlin@intel.com
      11ecbddd