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  1. Feb 01, 2018
    • Bjorn Helgaas's avatar
      Merge branch 'pci/dma' into next · ac7ab8a6
      Bjorn Helgaas authored
      * pci/dma:
        PCI: Remove NULL device handling from PCI DMA API
        net: tsi108: Use DMA API properly
        media: ttusb-dec: Remove pci_zalloc_coherent() abuse
        media: ttusb-budget: Remove pci_zalloc_coherent() abuse
      ac7ab8a6
    • Bjorn Helgaas's avatar
      Merge branch 'pci/deprecate-get-bus-and-slot' into next · b0b7f9cd
      Bjorn Helgaas authored
      * pci/deprecate-get-bus-and-slot:
        video: fbdev: riva: deprecate pci_get_bus_and_slot()
        video: fbdev: nvidia: deprecate pci_get_bus_and_slot()
        video: fbdev: intelfb: deprecate pci_get_bus_and_slot()
        openprom: Deprecate pci_get_bus_and_slot()
        xen/pcifront: Deprecate pci_get_bus_and_slot()
        PCI: Deprecate pci_get_bus_and_slot()
        PCI: ibmphp: Deprecate pci_get_bus_and_slot()
        PCI: cpqhp: Deprecate pci_get_bus_and_slot()
        pch_gbe: Deprecate pci_get_bus_and_slot()
        bnx2x: Deprecate pci_get_bus_and_slot()
        powerpc/via-pmu: Deprecate pci_get_bus_and_slot()
        iommu/amd: Deprecate pci_get_bus_and_slot()
        sl82c105: deprecate pci_get_bus_and_slot()
        drm/nouveau: deprecate pci_get_bus_and_slot()
        drm/gma500: Deprecate pci_get_bus_and_slot()
        ibft: Deprecate pci_get_bus_and_slot()
        edd: Deprecate pci_get_bus_and_slot()
        agp: sworks: Deprecate pci_get_bus_and_slot()
        agp: nvidia: Deprecate pci_get_bus_and_slot()
        ata: Deprecate pci_get_bus_and_slot()
        x86/PCI: Deprecate pci_get_bus_and_slot()
        powerpc/PCI: Deprecate pci_get_bus_and_slot()
        alpha/PCI: Deprecate pci_get_bus_and_slot()
      b0b7f9cd
    • Bjorn Helgaas's avatar
      Merge branch 'pci/aspm' into next · 3ea8bc33
      Bjorn Helgaas authored
      * pci/aspm:
        PCI/ASPM: Unexport internal ASPM interfaces
        PCI/ASPM: Enable Latency Tolerance Reporting when supported
        PCI/ASPM: Calculate LTR_L1.2_THRESHOLD from device characteristics
      3ea8bc33
    • Bjorn Helgaas's avatar
      Merge branch 'pci/aer' into next · 86e99150
      Bjorn Helgaas authored
      * pci/aer:
        PCI/AER: Return error if AER is not supported
        PCI/AER: Skip recovery callbacks for correctable errors from ACPI APEI
      86e99150
  2. Jan 18, 2018
  3. Jan 17, 2018
  4. Jan 12, 2018
  5. Dec 19, 2017
    • Bjorn Helgaas's avatar
      PCI/ASPM: Unexport internal ASPM interfaces · 7d8e7d19
      Bjorn Helgaas authored
      
      
      Several of the interfaces defined in include/linux/pci-aspm.h are used only
      internally from the PCI core:
      
        pcie_aspm_init_link_state()
        pcie_aspm_exit_link_state()
        pcie_aspm_pm_state_change()
        pcie_aspm_powersave_config_link()
        pcie_aspm_create_sysfs_dev_files()
        pcie_aspm_remove_sysfs_dev_files()
      
      Move these to the internal drivers/pci/pci.h header so they don't clutter
      the driver interface.
      
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      7d8e7d19
    • Bjorn Helgaas's avatar
      PCI/ASPM: Enable Latency Tolerance Reporting when supported · c46fd358
      Bjorn Helgaas authored
      
      
      Enable Latency Tolerance Reporting (LTR).  Note that LTR must be enabled in
      the Root Port first, and must not be enabled in any downstream device
      unless the Root Port and all intermediate Switches also support LTR.
      See PCIe r3.1, sec 6.18.
      
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: default avatarVidya Sagar <vidyas@nvidia.com>
      c46fd358
    • Bjorn Helgaas's avatar
      PCI/ASPM: Calculate LTR_L1.2_THRESHOLD from device characteristics · 80d7d7a9
      Bjorn Helgaas authored
      Per PCIe r3.1, sec 5.5.1, LTR_L1.2_THRESHOLD determines whether we enter
      the L1.2 Link state: if L1.2 is enabled and downstream devices have
      reported that they can tolerate latency of at least LTR_L1.2_THRESHOLD, we
      must enter L1.2 when CLKREQ# is de-asserted.
      
      The implication is that LTR_L1.2_THRESHOLD is the time required to
      transition the Link from L0 to L1.2 and back to L0, and per sec 5.5.3.3.1,
      Figures 5-16 and 5-17, it appears that the absolute minimum time for those
      transitions would be T(POWER_OFF) + T(L1.2) + T(POWER_ON) + T(COMMONMODE).
      
      Therefore, compute LTR_L1.2_THRESHOLD as:
      
          2us T(POWER_OFF)
        + 4us T(L1.2)
        + T(POWER_ON)
        + T(COMMONMODE)
        = LTR_L1.2_THRESHOLD
      
      Previously we set LTR_L1.2_THRESHOLD to a fixed value of 163840ns
      (163.84us):
      
        #define LTR_L1_2_THRESHOLD_BITS     ((1 << 21) | (1 << 23) | (1 << 30))
        ((1 << 21) | (1 << 23) | (1 << 30)) = 0x40a00000
        LTR_L1.2_THRESHOLD_Value = (0x40a00000 & 0x03ff0000) >> 16 = 0xa0 = 160
        LTR_L1.2_THRESHOLD_Scale = (0x40a00000 & 0xe0000000) >> 29 = 0x2 (* 1024ns)
        LTR_L1.2_THRESHOLD = 160 * 1024ns = 163840ns
      
      Obviously this doesn't account for the circuit characteristics of different
      implementations.
      
      Note that while firmware may enable LTR, Linux itself currently does not
      enable LTR.  When L1.2 is enabled but LTR is not, LTR_L1.2_THRESHOLD is
      ignored and we always enter L1.2 when it is enabled and CLKREQ# is
      de-asserted.  So this patch should not have any effect unless firmware
      enables LTR.
      
      Fixes: f1f0366d ("PCI/ASPM: Calculate and save the L1.2 timing parameters")
      Link: https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html
      
      
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: default avatarVidya Sagar <vidyas@nvidia.com>
      Cc: Kenji Chen <kenji.chen@intel.com>
      Cc: Patrick Georgi <pgeorgi@google.com>
      Cc: Rajat Jain <rajatja@google.com>
      80d7d7a9
    • Tyler Baicar's avatar
      PCI/AER: Skip recovery callbacks for correctable errors from ACPI APEI · b9f80fdc
      Tyler Baicar authored
      
      
      PCIe correctable errors are corrected by hardware.  Software may log them,
      but no other software intervention is required.
      
      There are two paths to enter the AER recovery code: (1) the native path
      where Linux fields the AER interrupt and reads the AER registers directly,
      and (2) the ACPI path where firmware reads the AER registers and hands them
      off to Linux via the ACPI APEI path.
      
      The AER do_recovery() function calls driver error reporting callbacks
      (error_detected(), mmio_enabled(), resume(), etc), attempts recovery (for
      fatal errors), and logs a "AER: Device recovery successful" message.
      
      Since there's nothing to recover for correctable errors, the native path
      already skips do_recovery(), so it doesn't call the driver callbacks and or
      emit the message.  Make the APEI path do the same.
      
      Signed-off-by: default avatarTyler Baicar <tbaicar@codeaurora.org>
      [bhelgaas: changelog]
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      b9f80fdc
  6. Dec 18, 2017