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    • Borislav Petkov's avatar
      kvm/emulate: Fix SETcc emulation function offsets with SLS · fe83f5ea
      Borislav Petkov authored
      The commit in Fixes started adding INT3 after RETs as a mitigation
      against straight-line speculation.
      
      The fastop SETcc implementation in kvm's insn emulator uses macro magic
      to generate all possible SETcc functions and to jump to them when
      emulating the respective instruction.
      
      However, it hardcodes the size and alignment of those functions to 4: a
      three-byte SETcc insn and a single-byte RET. BUT, with SLS, there's an
      INT3 that gets slapped after the RET, which brings the whole scheme out
      of alignment:
      
        15:   0f 90 c0                seto   %al
        18:   c3                      ret
        19:   cc                      int3
        1a:   0f 1f 00                nopl   (%rax)
        1d:   0f 91 c0                setno  %al
        20:   c3                      ret
        21:   cc                      int3
        22:   0f 1f 00                nopl   (%rax)
        25:   0f 92 c0                setb   %al
        28:   c3                      ret
        29:   cc                      int3
      
      and this explodes like this:
      
        int3: 0000 [#1] PREEMPT SMP PTI
        CPU: 0 PID: 2435 Comm: qemu-system-x86 Not tainted 5.17.0-rc8-sls #1
        Hardware name: Dell Inc. Precision WorkStation T3400  /0TP412, BIOS A14 04/30/2012
        RIP: 0010:setc+0x5/0x8 [kvm]
        Code: 00 00 0f 1f 00 0f b6 05 43 24 06 00 c3 cc 0f 1f 80 00 00 00 00 0f 90 c0 c3 cc 0f \
      	  1f 00 0f 91 c0 c3 cc 0f 1f 00 0f 92 c0 c3 cc <0f> 1f 00 0f 93 c0 c3 cc 0f 1f 00 \
      	  0f 94 c0 c3 cc 0f 1f 00 0f 95 c0
        Call Trace:
         <TASK>
         ? x86_emulate_insn [kvm]
         ? x86_emulate_instruction [kvm]
         ? vmx_handle_exit [kvm_intel]
         ? kvm_arch_vcpu_ioctl_run [kvm]
         ? kvm_vcpu_ioctl [kvm]
         ? __x64_sys_ioctl
         ? do_syscall_64
         ? entry_SYSCALL_64_after_hwframe
         </TASK>
      
      Raise the alignment value when SLS is enabled and use a macro for that
      instead of hard-coding naked numbers.
      
      Fixes: e463a09a
      
       ("x86: Add straight-line-speculation mitigation")
      Reported-by: default avatarJamie Heilman <jamie@audible.transient.net>
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Tested-by: default avatarJamie Heilman <jamie@audible.transient.net>
      Link: https://lore.kernel.org/r/YjGzJwjrvxg5YZ0Z@audible.transient.net
      
      
      [Add a comment and a bit of safety checking, since this is going to be changed
       again for IBT support. - Paolo]
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      fe83f5ea
    • Linus Torvalds's avatar
      Merge tag 'soc-fixes-5.17-4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc · 14702b3b
      Linus Torvalds authored
      Pull ARM SoC fix from Arnd Bergmann:
       "Here is one last regression fix for 5.17, reverting a patch that went
        into 5.16 as a cleanup that ended up breaking external interrupts on
        Layerscape chips.
      
        The revert makes it work again, but also reintroduces a build time
        warning about the nonstandard DT binding that will have to be dealt
        with in the future"
      
      * tag 'soc-fixes-5.17-4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
        Revert "arm64: dts: freescale: Fix 'interrupt-map' parent address cells"
      14702b3b