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  1. Feb 07, 2009
    • Len Brown's avatar
      ACPI: delete CPU_IDLE=n code · 9fdd54f2
      Len Brown authored 
      

CPU_IDLE=y has been default for ACPI=y since Nov-2007,
and has shipped in many distributions since then.

Here we delete the CPU_IDLE=n ACPI idle code, since
nobody should be using it, and we don't want to
maintain two versions.

Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      9fdd54f2
  3. Jan 29, 2009
    • Len Brown's avatar
      ACPI: remove BM_RLD access from idle entry path · 31878dd8
      Len Brown authored 
      It is true that BM_RLD needs to be set to enable
bus master activity to wake an older chipset (eg PIIX4) from C3.

This is contrary to the erroneous wording the ACPI 2.0, 3.0
specifications that suggests that BM_RLD is an indicator
rather than a control bit.

ACPI 1.0's correct wording should be restored in ACPI 4.0:
http://www.acpica.org/bugzilla/show_bug.cgi?id=689



But the kernel should not have to clear BM_RLD
when entering a non C3-type state just to set
it again when entering a C3-type C-state.

We should be able to set BM_RLD at boot time
and leave it alone -- removing the overhead of
accessing this IO register from the idle entry path.

Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      31878dd8
    • Len Brown's avatar
      ACPI: remove locking from PM1x_STS register reads · a2b7b01c
      Len Brown authored 
      

PM1a_STS and PM1b_STS are twins that get OR'd together
on reads, and all writes are repeated to both.

The fields in PM1x_STS are single bits only,
there are no multi-bit fields.

So it is not necessary to lock PM1x_STS reads against
writes because it is impossible to read an intermediate
value of a single bit.  It will either be 0 or 1,
even if a write is in progress during the read.
Reads are asynchronous to writes no matter if a lock
is used or not.

Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      a2b7b01c
  5. Jan 28, 2009